[llvm] [X86][MC] Compress APX Promoted instrs from evex to legacy encoding to save code size. (PR #77065)

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git-clang-format --diff f5f66e26b5f010218651cab831d5651fe7a71a0a 8d21f02c9ef42007ab487ac4f11e27ef15a65af3 -- llvm/lib/Target/X86/X86.h llvm/lib/Target/X86/X86InstrInfo.h llvm/lib/Target/X86/X86MCInstLower.cpp llvm/lib/Target/X86/X86TargetMachine.cpp llvm/lib/Target/X86/X86EvexToNonEvex.cpp llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/X86/X86EvexToNonEvex.cpp b/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
index 7eebb51e19..3c3f0bb412 100644
--- a/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
+++ b/llvm/lib/Target/X86/X86EvexToNonEvex.cpp
@@ -181,9 +181,10 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NonEvexOpc) {
   case X86::VSHUFI32X4Z256rri:
   case X86::VSHUFI64X2Z256rmi:
   case X86::VSHUFI64X2Z256rri: {
-    assert((NonEvexOpc == X86::VPERM2F128rr || NonEvexOpc == X86::VPERM2I128rr ||
-            NonEvexOpc == X86::VPERM2F128rm || NonEvexOpc == X86::VPERM2I128rm) &&
-           "Unexpected new opcode!");
+    assert(
+        (NonEvexOpc == X86::VPERM2F128rr || NonEvexOpc == X86::VPERM2I128rr ||
+         NonEvexOpc == X86::VPERM2F128rm || NonEvexOpc == X86::VPERM2I128rm) &&
+        "Unexpected new opcode!");
     MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
     int64_t ImmVal = Imm.getImm();
     // Set bit 5, move bit 1 to bit 4, copy bit 0.
@@ -206,7 +207,7 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NonEvexOpc) {
   case X86::VRNDSCALESDZm_Int:
   case X86::VRNDSCALESSZr_Int:
   case X86::VRNDSCALESSZm_Int:
-    const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands()-1);
+    const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
     int64_t ImmVal = Imm.getImm();
     // Ensure that only bits 3:0 of the immediate are used.
     if ((ImmVal & 0xf) != ImmVal)
@@ -273,7 +274,8 @@ static bool CompressEvexToVexImpl(MachineInstr &MI, const X86Subtarget &ST) {
 static bool CompressEVEX2LegacyImpl(MachineInstr &MI, const X86Subtarget &ST) {
   if (!ST.hasEGPR())
     return false;
-  ArrayRef<X86EvexToNonEvexCompressTableEntry> Table = X86EvexToLegacyCompressTable;
+  ArrayRef<X86EvexToNonEvexCompressTableEntry> Table =
+      X86EvexToLegacyCompressTable;
   unsigned EvexOpc = MI.getOpcode();
   const auto *I = llvm::lower_bound(Table, EvexOpc);
   if (I == Table.end() || I->EvexOpc != EvexOpc)
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index 685c033e10..316acdf25e 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -30,10 +30,10 @@ namespace X86 {
 
 enum AsmComments {
   // For instr that was compressed from EVEX to VEX.
-  AC_EVEX_2_VEX = MachineInstr::TAsmComments
-  , // For instrs that was compressed from ND to non-ND.
-  AC_ND_2_NONND = AC_EVEX_2_VEX << 1
-  , // For instrs that was compressed from EVEX to Legacy.
+  AC_EVEX_2_VEX = MachineInstr::TAsmComments, // For instrs that was compressed
+                                              // from ND to non-ND.
+  AC_ND_2_NONND = AC_EVEX_2_VEX
+                  << 1, // For instrs that was compressed from EVEX to Legacy.
   AC_EVEX_2_LEGACY = AC_ND_2_NONND << 1
 };
 
diff --git a/llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp
index ff8de47078..54c2564dd3 100644
--- a/llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86EVEX2NonEVEXTablesEmitter.cpp
@@ -72,16 +72,15 @@ private:
 };
 
 void X86EVEX2NonEVEXTablesEmitter::printTable(const std::vector<Entry> &Table,
-                                          raw_ostream &OS) {
+                                              raw_ostream &OS) {
 
   StringRef TargetEnc;
   StringRef TableName;
   StringRef Size;
-  if (Table == EVEX2LegacyTable){
+  if (Table == EVEX2LegacyTable) {
     TargetEnc = "Legacy";
     TableName = "X86EvexToLegacy";
-  }
-  else {
+  } else {
     TargetEnc = "VEX";
     TableName = "X86EvexToVex";
     Size = (Table == EVEX2VEX128) ? "128" : "256";
@@ -155,8 +154,8 @@ public:
     RecognizableInstrBase EVEXRI(*EVEXInst);
     bool VEX_W = VEXRI.HasREX_W;
     bool EVEX_W = EVEXRI.HasREX_W;
-    bool VEX_WIG  = VEXRI.IgnoresW;
-    bool EVEX_WIG  = EVEXRI.IgnoresW;
+    bool VEX_WIG = VEXRI.IgnoresW;
+    bool EVEX_WIG = EVEXRI.IgnoresW;
     bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0");
 
     if (VEXRI.IsCodeGenOnly != EVEXRI.IsCodeGenOnly ||
@@ -252,15 +251,15 @@ void X86EVEX2NonEVEXTablesEmitter::run(raw_ostream &OS) {
   }
 
   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
-    uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
-                                           getValueAsBitsInit("Opcode"));
+    uint64_t Opcode =
+        getValueFromBitsInit(EVEXInst->TheDef->getValueAsBitsInit("Opcode"));
     // For each EVEX instruction look for a VEX match in the appropriate vector
     // (instructions with the same opcode) using function object IsMatch.
     // Allow EVEX2VEXOverride to explicitly specify a match.
     const CodeGenInstruction *VEXInst = nullptr;
     if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
       StringRef AltInstStr =
-        EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
+          EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
       Record *AltInstRec = Records.getDef(AltInstStr);
       assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
       VEXInst = &Target.getInstruction(AltInstRec);

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https://github.com/llvm/llvm-project/pull/77065