[llvm] [RISCV] Don't attempt PRE if available info is SEW/LMUL ratio only (PR #77063)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/77063

We may attempt to do PRE on a block where one predecessor's exit info is
unknown, and one predecssor's exit info has the SEW/LMUL ratio only.

This should be avoided since we can't insert a vsetvli if we don't know its
exact VTYPE (yet).

Normally PRE would bail in these cases because coincidentally it wouldn't have
been profitable since not enough transitions would have been removed. However
after 6707b33, a PseudoVMV_X_S may now be enough to convince PRE that it is
indeed profitable, triggering the assertion when inserting vsetvli.

This fixes the issue described in
https://github.com/llvm/llvm-project/pull/74049#issuecomment-1878083020 by
bailing if the available info has the SEW/LMUL ratio only (i.e we don't know
the exact VTYPE)


>From 77e39d4deaa104b969a274a522dbb16596a2a721 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Fri, 5 Jan 2024 15:59:47 +0700
Subject: [PATCH] [RISCV] Don't attempt PRE if available info is SEW/LMUL ratio
 only

We may attempt to do PRE on a block where one predecessor's exit info is
unknown, and one predecssor's exit info has the SEW/LMUL ratio only.

This should be avoided since we can't insert a vsetvli if we don't know its
exact VTYPE (yet).

Normally PRE would bail in these cases because coincidentally it wouldn't have
been profitable since not enough transitions would have been removed. However
after 6707b33, a PseudoVMV_X_S may now be enough to convince PRE that it is
indeed profitable, triggering the assertion when inserting vsetvli.

This fixes the issue described in
https://github.com/llvm/llvm-project/pull/74049#issuecomment-1878083020 by
bailing if the available info has the SEW/LMUL ratio only (i.e we don't know
the exact VTYPE)
---
 llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp  |  5 ++
 .../test/CodeGen/RISCV/rvv/vsetvli-insert.mir | 57 +++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 3400b24e0abb01..e591aa935c0bfc 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1381,6 +1381,11 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
   if (!UnavailablePred || !AvailableInfo.isValid())
     return;
 
+  // If we don't know the exact VTYPE, we can't copy the vsetvli to the exit of
+  // the unavailable pred.
+  if (AvailableInfo.hasSEWLMULRatioOnly())
+    return;
+
   // Critical edge - TODO: consider splitting?
   if (UnavailablePred->succ_size() != 1)
     return;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 7bda7a387c68f9..d515022b74183b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -72,6 +72,10 @@
     ret void
   }
 
+  define void @pre_same_sewlmul_ratio() {
+    ret void
+  }
+
   declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
 
   declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
@@ -446,3 +450,56 @@ body:             |
     %4:vr = PseudoVMV_V_I_MF4 undef %4, 0, 4, 3, 0
     PseudoRET
 ...
+---
+# make sure we don't try to perform PRE when one of the blocks is sew/lmul ratio
+# only
+name: pre_same_sewlmul_ratio
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: pre_same_sewlmul_ratio
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %cond:gpr = COPY $x10
+  ; CHECK-NEXT:   dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
+  ; CHECK-NEXT:   [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+  ; CHECK-NEXT:   BEQ %cond, $x0, %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
+  ; CHECK-NEXT:   [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   BEQ %cond, $x0, %bb.4
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   successors: %bb.4(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   PseudoCALL $noreg, csr_ilp32_lp64
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype
+  ; CHECK-NEXT:   [[PseudoVMV_X_S_MF2_:%[0-9]+]]:gpr = PseudoVMV_X_S_MF2 $noreg, 5 /* e32 */, implicit $vtype
+  ; CHECK-NEXT:   [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    liveins: $x10
+    %cond:gpr = COPY $x10
+    %1:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5, 0
+    BEQ %cond, $x0, %bb.2
+  bb.1:
+    %2:vr = PseudoVMV_V_I_M1 $noreg, 1, 2, 6, 0
+  bb.2: ; the exit info here should have sew/lmul ratio only
+    BEQ %cond, $x0, %bb.4
+  bb.3:
+    PseudoCALL $noreg, csr_ilp32_lp64
+  bb.4: ; this block will have PRE attempted on it
+    %4:gpr = PseudoVMV_X_S_MF2 $noreg, 5
+    %5:vr = PseudoVMV_V_I_MF2 $noreg, 1, 2, 5, 0
+    PseudoRET
+...