[llvm] [RISCV] Codegen support for XCVmem extension (PR #76916)

[Liao Chunyu via llvm-commits]

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@@ -1210,7 +1210,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
   }
 
   void addRegRegOperands(MCInst &Inst, unsigned N) const {
-    assert(N == 1 && "Invalid number of operands!");
+    assert(N == 2 && "Invalid number of operands!");
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ChunyuLiao wrote:

I think it's because I'm using `let MIOperandInfo = (ops GPR:$base, GPR:$offset)` for CVrr operand, so it triggers the assert.

https://github.com/llvm/llvm-project/pull/76916