[llvm] [RISCV][NFC] Move Zawrs implementation to RISCVInstrInfoZawrs.td (PR #76940)
Wang Pengcheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 21:00:46 PST 2024
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/76940
>From 5a50374ce05c43d64148447c8d0bf908b5d68f4b Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 4 Jan 2024 19:17:45 +0800
Subject: [PATCH 1/3] [RISCV][NFC] Move Zawrs implementation to
RISCVInstrInfoZawrs.td
To keep the structure of TableGen files clear.
The definitions are simplified by the way.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 17 +------------
llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td | 26 ++++++++++++++++++++
2 files changed, 27 insertions(+), 16 deletions(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 35e8edf5d2fa72..066dd07a2ee7f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -729,22 +729,6 @@ def UNIMP : RVInstI<0b001, OPC_SYSTEM, (outs), (ins), "unimp", "">,
let imm12 = 0b110000000000;
}
-let Predicates = [HasStdExtZawrs] in {
-def WRS_NTO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.nto", "">,
- Sched<[]> {
- let rs1 = 0;
- let rd = 0;
- let imm12 = 0b000000001101;
-}
-
-def WRS_STO : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "wrs.sto", "">,
- Sched<[]> {
- let rs1 = 0;
- let rd = 0;
- let imm12 = 0b000000011101;
-}
-} // Predicates = [HasStdExtZawrs]
-
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
def CSRRW : CSR_ir<0b001, "csrrw">;
@@ -2095,6 +2079,7 @@ include "RISCVInstrInfoM.td"
// Atomic
include "RISCVInstrInfoA.td"
+include "RISCVInstrInfoZawrs.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
new file mode 100644
index 00000000000000..fac95eec814a46
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
@@ -0,0 +1,26 @@
+//===-- RISCVInstrInfoZawrs.td --------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard
+// Wait-on-Reservation-Set (Zawrs) extension document.
+//
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+class WRSInst<bits<12> funct12, string opcodestr>
+ : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
+ let rs1 = 0;
+ let rd = 0;
+ let imm12 = funct12;
+}
+}
+
+let Predicates = [HasStdExtZawrs] in {
+def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
+def WRS_STO : WRSInst<0b000000011101, "wrs.sto">, Sched<[]>;
+} // Predicates = [HasStdExtZawrs]
>From c6cd6f8a2999e0f9842f17cb1e67734dacce2c8b Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Thu, 4 Jan 2024 19:23:53 +0800
Subject: [PATCH 2/3] fixup! [RISCV][NFC] Move Zawrs implementation to
RISCVInstrInfoZawrs.td
Remove braces
---
llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
index fac95eec814a46..ad16d7daed74e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
@@ -11,14 +11,13 @@
//
//===----------------------------------------------------------------------===//
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class WRSInst<bits<12> funct12, string opcodestr>
: RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
let rs1 = 0;
let rd = 0;
let imm12 = funct12;
}
-}
let Predicates = [HasStdExtZawrs] in {
def WRS_NTO : WRSInst<0b000000001101, "wrs.nto">, Sched<[]>;
>From b5bc3c606702fce0c9fcbabb5f0ca445116cb0f5 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp at bytedance.com>
Date: Fri, 5 Jan 2024 12:34:32 +0800
Subject: [PATCH 3/3] Rename to RISCVInstrInfoZa.td
---
llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
.../{RISCVInstrInfoZawrs.td => RISCVInstrInfoZa.td} | 12 +++++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
rename llvm/lib/Target/RISCV/{RISCVInstrInfoZawrs.td => RISCVInstrInfoZa.td} (72%)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 066dd07a2ee7f0..2f4744529469bd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2079,7 +2079,7 @@ include "RISCVInstrInfoM.td"
// Atomic
include "RISCVInstrInfoA.td"
-include "RISCVInstrInfoZawrs.td"
+include "RISCVInstrInfoZa.td"
// Scalar FP
include "RISCVInstrInfoF.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
similarity index 72%
rename from llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
rename to llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
index ad16d7daed74e1..ed2fd4f1092a47 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZawrs.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -1,4 +1,4 @@
-//===-- RISCVInstrInfoZawrs.td --------------------------------------------===//
+//===-- RISCVInstrInfoZa.td - RISC-V Atomic instructions ---*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,11 +6,17 @@
//
//===----------------------------------------------------------------------===//
//
-// This file describes the RISC-V instructions from the standard
-// Wait-on-Reservation-Set (Zawrs) extension document.
+// This file describes the RISC-V instructions from the standard atomic 'Za*'
+// extensions:
+// - Zawrs (v1.0) : Wait-on-Reservation-Set.
//
//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Zawrs (Wait-on-Reservation-Set)
+//===----------------------------------------------------------------------===//
+
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
class WRSInst<bits<12> funct12, string opcodestr>
: RVInstI<0b000, OPC_SYSTEM, (outs), (ins), opcodestr, ""> {
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