[llvm] 4768563 - AMDGPU: Make v4bf16 a legal type (#76217)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 17:35:12 PST 2024
Author: Matt Arsenault
Date: 2024-01-05T08:35:07+07:00
New Revision: 47685633a7dc74451acbc551b111929166d4d0bd
URL: https://github.com/llvm/llvm-project/commit/47685633a7dc74451acbc551b111929166d4d0bd
DIFF: https://github.com/llvm/llvm-project/commit/47685633a7dc74451acbc551b111929166d4d0bd.diff
LOG: AMDGPU: Make v4bf16 a legal type (#76217)
Gets a few code quality improvements. A few cases are worse
from losing load narrowing.
Depends #76213 #76214 #76215
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/bf16.ll
llvm/test/CodeGen/AMDGPU/function-args.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
llvm/test/CodeGen/AMDGPU/select-undef.ll
llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index b70d33d58b7485..2f663571a8f97b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -389,15 +389,16 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
Custom);
setOperationAction(
ISD::EXTRACT_SUBVECTOR,
- {MVT::v2f16, MVT::v2i16, MVT::v4f16, MVT::v4i16, MVT::v2f32,
- MVT::v2i32, MVT::v3f32, MVT::v3i32, MVT::v4f32, MVT::v4i32,
- MVT::v5f32, MVT::v5i32, MVT::v6f32, MVT::v6i32, MVT::v7f32,
- MVT::v7i32, MVT::v8f32, MVT::v8i32, MVT::v9f32, MVT::v9i32,
- MVT::v10i32, MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32,
- MVT::v12f32, MVT::v16f16, MVT::v16i16, MVT::v16f32, MVT::v16i32,
- MVT::v32f32, MVT::v32i32, MVT::v2f64, MVT::v2i64, MVT::v3f64,
- MVT::v3i64, MVT::v4f64, MVT::v4i64, MVT::v8f64, MVT::v8i64,
- MVT::v16f64, MVT::v16i64, MVT::v32i16, MVT::v32f16},
+ {MVT::v2f16, MVT::v2i16, MVT::v2bf16, MVT::v4f16, MVT::v4i16,
+ MVT::v4bf16, MVT::v2f32, MVT::v2i32, MVT::v3f32, MVT::v3i32,
+ MVT::v4f32, MVT::v4i32, MVT::v5f32, MVT::v5i32, MVT::v6f32,
+ MVT::v6i32, MVT::v7f32, MVT::v7i32, MVT::v8f32, MVT::v8i32,
+ MVT::v9f32, MVT::v9i32, MVT::v10i32, MVT::v10f32, MVT::v11i32,
+ MVT::v11f32, MVT::v12i32, MVT::v12f32, MVT::v16f16, MVT::v16i16,
+ MVT::v16f32, MVT::v16i32, MVT::v32f32, MVT::v32i32, MVT::v2f64,
+ MVT::v2i64, MVT::v3f64, MVT::v3i64, MVT::v4f64, MVT::v4i64,
+ MVT::v8f64, MVT::v8i64, MVT::v16f64, MVT::v16i64, MVT::v32i16,
+ MVT::v32f16},
Custom);
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index a89ef658734b2f..c84a0934ca8138 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -164,6 +164,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
addRegisterClass(MVT::v2bf16, &AMDGPU::SReg_32RegClass);
addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
+ addRegisterClass(MVT::v4bf16, &AMDGPU::SReg_64RegClass);
addRegisterClass(MVT::v8i16, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v8f16, &AMDGPU::SGPR_128RegClass);
addRegisterClass(MVT::v16i16, &AMDGPU::SGPR_256RegClass);
@@ -312,10 +313,10 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
{MVT::v8i32, MVT::v8f32, MVT::v9i32, MVT::v9f32, MVT::v10i32,
MVT::v10f32, MVT::v11i32, MVT::v11f32, MVT::v12i32, MVT::v12f32,
MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64, MVT::v4i16,
- MVT::v4f16, MVT::v3i64, MVT::v3f64, MVT::v6i32, MVT::v6f32,
- MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64, MVT::v8i16,
- MVT::v8f16, MVT::v16i16, MVT::v16f16, MVT::v16i64, MVT::v16f64,
- MVT::v32i32, MVT::v32f32, MVT::v32i16, MVT::v32f16}) {
+ MVT::v4f16, MVT::v4bf16, MVT::v3i64, MVT::v3f64, MVT::v6i32,
+ MVT::v6f32, MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
+ MVT::v8i16, MVT::v8f16, MVT::v16i16, MVT::v16f16, MVT::v16i64,
+ MVT::v16f64, MVT::v32i32, MVT::v32f32, MVT::v32i16, MVT::v32f16}) {
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
switch (Op) {
case ISD::LOAD:
@@ -421,13 +422,14 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
{MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32},
Expand);
- setOperationAction(ISD::BUILD_VECTOR, {MVT::v4f16, MVT::v4i16}, Custom);
+ setOperationAction(ISD::BUILD_VECTOR, {MVT::v4f16, MVT::v4i16, MVT::v4bf16},
+ Custom);
// Avoid stack access for these.
// TODO: Generalize to more vector types.
setOperationAction({ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT},
{MVT::v2i16, MVT::v2f16, MVT::v2bf16, MVT::v2i8, MVT::v4i8,
- MVT::v8i8, MVT::v4i16, MVT::v4f16},
+ MVT::v8i8, MVT::v4i16, MVT::v4f16, MVT::v4bf16},
Custom);
// Deal with vec3 vector operations when widened to vec4.
@@ -667,11 +669,15 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
+ setOperationAction(ISD::LOAD, MVT::v4bf16, Promote);
+ AddPromotedToType(ISD::LOAD, MVT::v4bf16, MVT::v2i32);
setOperationAction(ISD::STORE, MVT::v4i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
setOperationAction(ISD::STORE, MVT::v4f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
+ setOperationAction(ISD::STORE, MVT::v4bf16, Promote);
+ AddPromotedToType(ISD::STORE, MVT::v4bf16, MVT::v2i32);
setOperationAction(ISD::LOAD, MVT::v8i16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v8i16, MVT::v4i32);
@@ -781,7 +787,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
Custom);
setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
- setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16}, Custom);
+ setOperationAction(ISD::SELECT, {MVT::v4i16, MVT::v4f16, MVT::v4bf16},
+ Custom);
if (Subtarget->hasPackedFP32Ops()) {
setOperationAction({ISD::FADD, ISD::FMUL, ISD::FMA, ISD::FNEG},
@@ -6805,7 +6812,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
SDLoc SL(Op);
EVT VT = Op.getValueType();
- if (VT == MVT::v4i16 || VT == MVT::v4f16 ||
+ if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16 ||
VT == MVT::v8i16 || VT == MVT::v8f16) {
EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(),
VT.getVectorNumElements() / 2);
@@ -6871,7 +6878,7 @@ SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
}
- assert(VT == MVT::v2f16 || VT == MVT::v2i16);
+ assert(VT == MVT::v2f16 || VT == MVT::v2i16 || VT == MVT::v2bf16);
assert(!Subtarget->hasVOP3PInsts() && "this should be legal");
SDValue Lo = Op.getOperand(0);
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index c2992060796708..e8c4d805dbba9e 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -1548,6 +1548,19 @@ def : BitConvert <f64, v2i32, VReg_64>;
def : BitConvert <v2i32, f64, VReg_64>;
def : BitConvert <v4i16, v4f16, VReg_64>;
def : BitConvert <v4f16, v4i16, VReg_64>;
+def : BitConvert <v4bf16, v2i32, VReg_64>;
+def : BitConvert <v2i32, v4bf16, VReg_64>;
+def : BitConvert <v4bf16, i64, VReg_64>;
+def : BitConvert <i64, v4bf16, VReg_64>;
+def : BitConvert <v4bf16, v4i16, VReg_64>;
+def : BitConvert <v4i16, v4bf16, VReg_64>;
+def : BitConvert <v4bf16, v4f16, VReg_64>;
+def : BitConvert <v4f16, v4bf16, VReg_64>;
+def : BitConvert <v4bf16, v2f32, VReg_64>;
+def : BitConvert <v2f32, v4bf16, VReg_64>;
+def : BitConvert <v4bf16, f64, VReg_64>;
+def : BitConvert <f64, v4bf16, VReg_64>;
+
// FIXME: Make SGPR
def : BitConvert <v2i32, v4f16, VReg_64>;
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 5243262117e728..2a3417e2418552 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -4133,9 +4133,7 @@ define void @test_call_v4bf16(<4 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v3, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: scratch_store_b32 v2, v1, off offset:4 dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v2, v0, off dlc
+; GFX11-NEXT: scratch_store_b64 v2, v[0:1], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: v_readlane_b32 s31, v3, 1
; GFX11-NEXT: v_readlane_b32 s30, v3, 0
@@ -4397,18 +4395,12 @@ define void @test_call_v8bf16(<8 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v5, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 12, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_readlane_b32 s31, v5, 1
-; GFX11-NEXT: v_readlane_b32 s30, v5, 0
-; GFX11-NEXT: scratch_store_b32 v6, v3, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v4, v2, off offset:8 dlc
+; GFX11-NEXT: scratch_store_b64 v4, v[2:3], off offset:8 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v4, v1, off offset:4 dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v4, v0, off dlc
+; GFX11-NEXT: scratch_store_b64 v4, v[0:1], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_readlane_b32 s31, v5, 1
+; GFX11-NEXT: v_readlane_b32 s30, v5, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v5, off, s33 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -4759,28 +4751,18 @@ define void @test_call_v16bf16(<16 x bfloat> %in, ptr addrspace(5) %out) {
; GFX11-NEXT: v_writelane_b32 v9, s31, 1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_swappc_b64 s[30:31], s[0:1]
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 28, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v11, 24, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v12, 20, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 12, v8
+; GFX11-NEXT: v_add_nc_u32_e32 v10, 24, v8
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_readlane_b32 s31, v9, 1
-; GFX11-NEXT: scratch_store_b32 v10, v7, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v11, v6, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v12, v5, off dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v8, v4, off offset:16 dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v13, v3, off dlc
+; GFX11-NEXT: v_readlane_b32 s30, v9, 0
+; GFX11-NEXT: scratch_store_b64 v10, v[6:7], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v8, v2, off offset:8 dlc
+; GFX11-NEXT: scratch_store_b64 v8, v[4:5], off offset:16 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v8, v1, off offset:4 dlc
+; GFX11-NEXT: scratch_store_b64 v8, v[2:3], off offset:8 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: scratch_store_b32 v8, v0, off dlc
+; GFX11-NEXT: scratch_store_b64 v8, v[0:1], off dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: v_readlane_b32 s30, v9, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v9, off, s33 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -8691,83 +8673,52 @@ define <3 x bfloat> @v_fadd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX8-LABEL: v_fadd_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f32_e32 v3, v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_add_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fadd_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_add_f32_e32 v3, v4, v3
; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_add_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fadd_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_add_f32_e32 v4, v5, v4
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_f32_e32 v2, v7, v6
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fadd_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_add_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <3 x bfloat> %a, %b
ret <3 x bfloat> %op
}
@@ -8818,82 +8769,81 @@ define <4 x bfloat> @v_fadd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX8-LABEL: v_fadd_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_add_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_add_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fadd_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_add_f32_e32 v3, v5, v3
; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_add_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fadd_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_add_f32_e32 v5, v7, v6
; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_add_f32_e32 v2, v7, v6
; GFX10-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fadd_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_add_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_dual_add_f32 v4, v5, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_add_f32_e32 v5, v7, v6
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <4 x bfloat> %a, %b
ret <4 x bfloat> %op
@@ -8977,138 +8927,138 @@ define <8 x bfloat> @v_fadd_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX8-LABEL: v_fadd_v8bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_add_f32_e32 v7, v9, v7
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_add_f32_e32 v6, v9, v6
; GFX8-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX8-NEXT: v_add_f32_e32 v4, v8, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX8-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v5, v9, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v5, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v7, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fadd_v8bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_add_f32_e32 v7, v9, v7
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_add_f32_e32 v6, v9, v6
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_add_f32_e32 v5, v9, v5
; GFX9-NEXT: v_add_f32_e32 v0, v0, v4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_add_f32_e32 v4, v8, v4
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v5
-; GFX9-NEXT: v_perm_b32 v2, v2, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_add_f32_e32 v3, v3, v5
-; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v5, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v7, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fadd_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_add_f32_e32 v8, v9, v8
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_add_f32_e32 v9, v11, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_add_f32_e32 v8, v9, v8
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_add_f32_e32 v4, v11, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_add_f32_e32 v10, v11, v10
+; GFX10-NEXT: v_add_f32_e32 v11, v13, v12
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_add_f32_e32 v5, v10, v9
; GFX10-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX10-NEXT: v_add_f32_e32 v6, v12, v11
; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX10-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fadd_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_add_f32 v9, v11, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_add_f32_e32 v4, v11, v10
-; GFX11-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_add_f32_e32 v5, v10, v9
-; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX11-NEXT: v_add_f32_e32 v6, v12, v11
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v5 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v6 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX11-NEXT: v_dual_add_f32 v10, v11, v10 :: v_dual_add_f32 v11, v13, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <8 x bfloat> %a, %b
ret <8 x bfloat> %op
@@ -9260,252 +9210,254 @@ define <16 x bfloat> @v_fadd_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX8-LABEL: v_fadd_v16bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX8-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v7, v7, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_add_f32_e32 v15, v17, v15
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_add_f32_e32 v14, v17, v14
+; GFX8-NEXT: v_add_f32_e32 v5, v5, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_add_f32_e32 v13, v17, v13
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_add_f32_e32 v12, v17, v12
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_add_f32_e32 v11, v17, v11
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_add_f32_e32 v10, v17, v10
; GFX8-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX8-NEXT: v_add_f32_e32 v8, v16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_add_f32_e32 v3, v3, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_add_f32_e32 v4, v4, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_add_f32_e32 v5, v5, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX8-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_add_f32_e32 v7, v7, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v9, v17, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v9, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v10, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v11, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v12, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v13, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v14, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v15, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fadd_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_add_f32_e32 v7, v7, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_add_f32_e32 v15, v17, v15
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_add_f32_e32 v14, v17, v14
+; GFX9-NEXT: v_add_f32_e32 v5, v5, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_add_f32_e32 v13, v17, v13
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_add_f32_e32 v12, v17, v12
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_add_f32_e32 v11, v17, v11
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_add_f32_e32 v10, v17, v10
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v8
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v0
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_add_f32_e32 v9, v17, v9
; GFX9-NEXT: v_add_f32_e32 v0, v0, v8
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_add_f32_e32 v8, v16, v8
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX9-NEXT: v_perm_b32 v1, v1, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v9
-; GFX9-NEXT: v_perm_b32 v2, v2, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_add_f32_e32 v3, v3, v9
-; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_add_f32_e32 v4, v4, v9
-; GFX9-NEXT: v_perm_b32 v4, v4, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
-; GFX9-NEXT: v_perm_b32 v5, v5, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v9
-; GFX9-NEXT: v_perm_b32 v6, v6, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_add_f32_e32 v7, v7, v9
-; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v9, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v11, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v13, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fadd_v16bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v5
; GFX10-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX10-NEXT: v_add_f32_e32 v7, v7, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX10-NEXT: v_add_f32_e32 v15, v17, v15
+; GFX10-NEXT: v_add_f32_e32 v6, v6, v14
+; GFX10-NEXT: v_add_f32_e32 v14, v19, v18
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v13
+; GFX10-NEXT: v_add_f32_e32 v13, v21, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_add_f32_e32 v17, v18, v17
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_add_f32_e32 v18, v20, v19
; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX10-NEXT: v_add_f32_e32 v19, v20, v19
+; GFX10-NEXT: v_add_f32_e32 v20, v22, v21
; GFX10-NEXT: v_add_f32_e32 v0, v0, v8
-; GFX10-NEXT: v_add_f32_e32 v8, v18, v17
; GFX10-NEXT: v_add_f32_e32 v1, v1, v9
-; GFX10-NEXT: v_add_f32_e32 v9, v20, v19
; GFX10-NEXT: v_add_f32_e32 v2, v2, v10
-; GFX10-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11
-; GFX10-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX10-NEXT: v_add_f32_e32 v8, v9, v8
-; GFX10-NEXT: v_add_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_add_f32_e32 v9, v16, v11
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v11
; GFX10-NEXT: v_add_f32_e32 v4, v4, v12
-; GFX10-NEXT: v_add_f32_e32 v10, v18, v17
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_add_f32_e32 v5, v5, v11
-; GFX10-NEXT: v_add_f32_e32 v11, v13, v12
-; GFX10-NEXT: v_add_f32_e32 v6, v6, v14
-; GFX10-NEXT: v_add_f32_e32 v12, v17, v16
-; GFX10-NEXT: v_add_f32_e32 v7, v7, v15
-; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX10-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fadd_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v10
-; GFX11-NEXT: v_dual_add_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v9 :: v_dual_and_b32 v10, 0xffff0000, v11
-; GFX11-NEXT: v_add_f32_e32 v9, v20, v19
-; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v8
-; GFX11-NEXT: v_add_f32_e32 v8, v18, v17
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_dual_add_f32 v10, v18, v17 :: v_dual_lshlrev_b32 v17, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_add_f32 v4, v4, v12 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_dual_add_f32 v8, v9, v8 :: v_dual_add_f32 v9, v16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v4, v4, v12 :: v_dual_and_b32 v5, 0xffff0000, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: v_add_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_add_f32_e32 v13, v21, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_dual_add_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: v_add_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11-NEXT: v_add_f32_e32 v5, v5, v11
-; GFX11-NEXT: v_add_f32_e32 v11, v13, v12
-; GFX11-NEXT: v_add_f32_e32 v12, v17, v16
-; GFX11-NEXT: v_dual_add_f32 v6, v6, v14 :: v_dual_add_f32 v7, v7, v15
-; GFX11-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-NEXT: v_add_f32_e32 v15, v17, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v6, v6, v14 :: v_dual_lshlrev_b32 v17, 16, v11
+; GFX11-NEXT: v_add_f32_e32 v14, v19, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v17, v18, v17 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-NEXT: v_add_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_dual_add_f32 v18, v20, v19 :: v_dual_lshlrev_b32 v19, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_add_f32 v19, v20, v19 :: v_dual_add_f32 v20, v22, v21
+; GFX11-NEXT: v_add_f32_e32 v1, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <16 x bfloat> %a, %b
ret <16 x bfloat> %op
@@ -9913,483 +9865,480 @@ define <32 x bfloat> @v_fadd_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX8-LABEL: v_fadd_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX8-NEXT: v_add_f32_e32 v31, v32, v31
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX8-NEXT: v_add_f32_e32 v30, v14, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_add_f32_e32 v14, v32, v14
+; GFX8-NEXT: v_add_f32_e32 v13, v13, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_add_f32_e32 v29, v32, v29
+; GFX8-NEXT: v_add_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_add_f32_e32 v28, v32, v28
+; GFX8-NEXT: v_add_f32_e32 v11, v11, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_add_f32_e32 v27, v32, v27
+; GFX8-NEXT: v_add_f32_e32 v10, v10, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX8-NEXT: v_add_f32_e32 v26, v32, v26
+; GFX8-NEXT: v_add_f32_e32 v9, v9, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_add_f32_e32 v8, v8, v24
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX8-NEXT: v_add_f32_e32 v25, v32, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16
+; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16
+; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16
+; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16
+; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16
+; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_add_f32_e32 v32, v32, v33
+; GFX8-NEXT: v_add_f32_e32 v15, v15, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_add_f32_e32 v24, v33, v24
+; GFX8-NEXT: v_add_f32_e32 v7, v7, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_add_f32_e32 v23, v33, v23
+; GFX8-NEXT: v_add_f32_e32 v6, v6, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_add_f32_e32 v22, v33, v22
+; GFX8-NEXT: v_add_f32_e32 v5, v5, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_add_f32_e32 v21, v33, v21
+; GFX8-NEXT: v_add_f32_e32 v4, v4, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_add_f32_e32 v20, v33, v20
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_add_f32_e32 v19, v33, v19
+; GFX8-NEXT: v_add_f32_e32 v2, v2, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_add_f32_e32 v18, v33, v18
; GFX8-NEXT: v_add_f32_e32 v1, v1, v17
-; GFX8-NEXT: v_add_f32_e32 v16, v31, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_add_f32_e32 v17, v33, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX8-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX8-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_add_f32_e32 v3, v3, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX8-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_add_f32_e32 v4, v4, v17
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_add_f32_e32 v5, v5, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_add_f32_e32 v7, v7, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_add_f32_e32 v8, v8, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX8-NEXT: v_add_f32_e32 v9, v9, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
-; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX8-NEXT: v_add_f32_e32 v10, v10, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27
-; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX8-NEXT: v_add_f32_e32 v11, v11, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
-; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX8-NEXT: v_add_f32_e32 v12, v12, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29
-; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX8-NEXT: v_add_f32_e32 v13, v13, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX8-NEXT: v_add_f32_e32 v14, v14, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX8-NEXT: v_add_f32_e32 v15, v15, v17
-; GFX8-NEXT: v_add_f32_e32 v16, v18, v16
; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16
+; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16
+; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fadd_v32bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX9-NEXT: v_add_f32_e32 v31, v32, v31
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_add_f32_e32 v14, v14, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_add_f32_e32 v30, v32, v30
+; GFX9-NEXT: v_add_f32_e32 v13, v13, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_add_f32_e32 v29, v32, v29
+; GFX9-NEXT: v_add_f32_e32 v12, v12, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_add_f32_e32 v28, v32, v28
+; GFX9-NEXT: v_add_f32_e32 v11, v11, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_add_f32_e32 v27, v32, v27
+; GFX9-NEXT: v_add_f32_e32 v10, v10, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_add_f32_e32 v26, v32, v26
+; GFX9-NEXT: v_add_f32_e32 v9, v9, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX9-NEXT: v_add_f32_e32 v8, v8, v24
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX9-NEXT: v_add_f32_e32 v25, v32, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4
+; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4
+; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4
+; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4
+; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_add_f32_e32 v32, v32, v33
+; GFX9-NEXT: v_add_f32_e32 v15, v15, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_add_f32_e32 v24, v33, v24
+; GFX9-NEXT: v_add_f32_e32 v7, v7, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_add_f32_e32 v23, v33, v23
+; GFX9-NEXT: v_add_f32_e32 v6, v6, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_add_f32_e32 v22, v33, v22
+; GFX9-NEXT: v_add_f32_e32 v5, v5, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_add_f32_e32 v21, v33, v21
+; GFX9-NEXT: v_add_f32_e32 v4, v4, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_add_f32_e32 v20, v33, v20
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_add_f32_e32 v19, v33, v19
+; GFX9-NEXT: v_add_f32_e32 v2, v2, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_add_f32_e32 v16, v31, v16
+; GFX9-NEXT: v_add_f32_e32 v18, v33, v18
; GFX9-NEXT: v_add_f32_e32 v1, v1, v17
-; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v17
-; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_add_f32_e32 v3, v3, v17
-; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_add_f32_e32 v4, v4, v17
-; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_add_f32_e32 v5, v5, v17
-; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v17
-; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_add_f32_e32 v7, v7, v17
-; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24
-; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX9-NEXT: v_add_f32_e32 v8, v8, v17
-; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_add_f32_e32 v9, v9, v17
-; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26
-; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX9-NEXT: v_add_f32_e32 v10, v10, v17
-; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27
-; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX9-NEXT: v_add_f32_e32 v11, v11, v17
-; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28
-; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX9-NEXT: v_add_f32_e32 v12, v12, v17
-; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29
-; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX9-NEXT: v_add_f32_e32 v13, v13, v17
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30
-; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX9-NEXT: v_add_f32_e32 v14, v14, v17
-; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX9-NEXT: v_add_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX9-NEXT: v_add_f32_e32 v15, v15, v17
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_add_f32_e32 v17, v33, v17
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fadd_v32bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_add_f32_e32 v39, v48, v39
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17
+; GFX10-NEXT: v_add_f32_e32 v11, v11, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_add_f32_e32 v5, v5, v21
-; GFX10-NEXT: v_add_f32_e32 v21, v53, v52
-; GFX10-NEXT: v_add_f32_e32 v6, v6, v22
-; GFX10-NEXT: v_add_f32_e32 v22, v55, v54
-; GFX10-NEXT: v_add_f32_e32 v7, v7, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9
+; GFX10-NEXT: v_add_f32_e32 v49, v50, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16
+; GFX10-NEXT: v_add_f32_e32 v10, v10, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9
; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX10-NEXT: v_add_f32_e32 v32, v33, v32
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10
-; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_add_f32_e32 v33, v34, v33
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20
+; GFX10-NEXT: v_add_f32_e32 v14, v14, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_add_f32_e32 v35, v36, v35
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX10-NEXT: v_add_f32_e32 v13, v13, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3
+; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_add_f32_e32 v37, v38, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18
+; GFX10-NEXT: v_add_f32_e32 v12, v12, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX10-NEXT: v_add_f32_e32 v34, v35, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX10-NEXT: v_add_f32_e32 v1, v1, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28
-; GFX10-NEXT: v_add_f32_e32 v36, v37, v36
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12
-; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_add_f32_e32 v51, v52, v51
+; GFX10-NEXT: v_add_f32_e32 v9, v9, v25
+; GFX10-NEXT: v_add_f32_e32 v25, v54, v53
+; GFX10-NEXT: v_add_f32_e32 v8, v8, v24
+; GFX10-NEXT: v_add_f32_e32 v24, v64, v55
+; GFX10-NEXT: v_add_f32_e32 v7, v7, v23
+; GFX10-NEXT: v_add_f32_e32 v23, v66, v65
+; GFX10-NEXT: v_add_f32_e32 v6, v6, v22
+; GFX10-NEXT: v_add_f32_e32 v22, v68, v67
+; GFX10-NEXT: v_add_f32_e32 v5, v5, v21
+; GFX10-NEXT: v_add_f32_e32 v21, v30, v34
+; GFX10-NEXT: v_add_f32_e32 v29, v29, v36
+; GFX10-NEXT: v_add_f32_e32 v28, v28, v38
+; GFX10-NEXT: v_add_f32_e32 v27, v27, v48
+; GFX10-NEXT: v_add_f32_e32 v26, v26, v50
; GFX10-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; GFX10-NEXT: v_add_f32_e32 v38, v39, v38
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13
-; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX10-NEXT: v_add_f32_e32 v3, v3, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30
-; GFX10-NEXT: v_add_f32_e32 v48, v49, v48
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14
-; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX10-NEXT: v_add_f32_e32 v4, v4, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX10-NEXT: v_add_f32_e32 v50, v51, v50
-; GFX10-NEXT: v_add_f32_e32 v23, v65, v64
-; GFX10-NEXT: v_add_f32_e32 v8, v8, v24
-; GFX10-NEXT: v_add_f32_e32 v24, v67, v66
-; GFX10-NEXT: v_add_f32_e32 v9, v9, v25
-; GFX10-NEXT: v_add_f32_e32 v25, v33, v68
-; GFX10-NEXT: v_add_f32_e32 v10, v10, v26
-; GFX10-NEXT: v_add_f32_e32 v16, v35, v16
-; GFX10-NEXT: v_add_f32_e32 v11, v11, v27
-; GFX10-NEXT: v_add_f32_e32 v17, v37, v17
-; GFX10-NEXT: v_add_f32_e32 v12, v12, v28
-; GFX10-NEXT: v_add_f32_e32 v18, v39, v18
-; GFX10-NEXT: v_add_f32_e32 v13, v13, v29
-; GFX10-NEXT: v_add_f32_e32 v19, v49, v19
-; GFX10-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302
-; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302
-; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302
+; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302
+; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302
+; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302
+; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302
+; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31
-; GFX10-NEXT: v_add_f32_e32 v20, v20, v21
-; GFX10-NEXT: v_add_f32_e32 v15, v15, v22
-; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX10-NEXT: v_add_f32_e32 v16, v32, v16
+; GFX10-NEXT: v_add_f32_e32 v15, v15, v17
+; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fadd_v32bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10
-; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX11-NEXT: v_dual_add_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28
-; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10
+; GFX11-NEXT: v_dual_add_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_dual_add_f32 v2, v2, v18 :: v_dual_add_f32 v3, v3, v19
+; GFX11-NEXT: v_dual_add_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26
+; GFX11-NEXT: v_dual_add_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_add_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_dual_add_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28
; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_f32_e32 v10, v10, v26
+; GFX11-NEXT: v_add_f32_e32 v26, v52, v51
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_add_f32_e32 v25, v54, v53
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30
-; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_dual_add_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4
-; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_add_f32_e32 v4, v4, v20
-; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_add_f32 v9, v9, v25
-; GFX11-NEXT: v_add_f32_e32 v25, v69, v68
-; GFX11-NEXT: v_dual_add_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3
-; GFX11-NEXT: v_add_f32_e32 v27, v81, v80
-; GFX11-NEXT: v_add_f32_e32 v12, v12, v28
-; GFX11-NEXT: v_dual_add_f32 v28, v83, v82 :: v_dual_add_f32 v29, v85, v84
-; GFX11-NEXT: v_dual_add_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_add_f32_e32 v22, v55, v54
-; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_dual_add_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_add_f32_e32 v24, v64, v55
+; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_add_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_add_f32_e32 v23, v66, v65
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_dual_add_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_add_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-NEXT: v_dual_add_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_add_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: v_add_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_add_f32_e32 v37, v86, v85
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11-NEXT: v_add_f32_e32 v14, v14, v30
-; GFX11-NEXT: v_dual_add_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_add_f32_e32 v23, v65, v64
-; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT: v_dual_add_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21
-; GFX11-NEXT: v_add_f32_e32 v2, v2, v18
-; GFX11-NEXT: v_dual_add_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16
-; GFX11-NEXT: v_add_f32_e32 v18, v39, v38
-; GFX11-NEXT: v_dual_add_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16
-; GFX11-NEXT: v_add_f32_e32 v19, v49, v48
-; GFX11-NEXT: v_add_f32_e32 v17, v37, v36
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX11-NEXT: v_dual_add_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_add_f32_e32 v21, v53, v52
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302
-; GFX11-NEXT: v_add_f32_e32 v0, v0, v16
-; GFX11-NEXT: v_add_f32_e32 v16, v35, v34
-; GFX11-NEXT: v_add_f32_e32 v32, v33, v32
-; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302
-; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302
-; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302
-; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_add_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31
-; GFX11-NEXT: v_add_f32_e32 v15, v15, v17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_add_f32 v30, v36, v35 :: v_dual_add_f32 v33, v34, v33
+; GFX11-NEXT: v_dual_add_f32 v34, v80, v71 :: v_dual_add_f32 v35, v82, v81
+; GFX11-NEXT: v_add_f32_e32 v36, v84, v83
+; GFX11-NEXT: v_dual_add_f32 v16, v32, v16 :: v_dual_add_f32 v15, v15, v17
+; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fadd <32 x bfloat> %a, %b
@@ -10681,83 +10630,52 @@ define <3 x bfloat> @v_fsub_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX8-LABEL: v_fsub_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_sub_f32_e32 v3, v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fsub_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v4, v3
; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fsub_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_f32_e32 v2, v7, v6
; GFX10-NEXT: v_sub_f32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fsub_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_sub_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fsub <3 x bfloat> %a, %b
ret <3 x bfloat> %op
}
@@ -10808,82 +10726,81 @@ define <4 x bfloat> @v_fsub_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX8-LABEL: v_fsub_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_sub_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_sub_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fsub_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_f32_e32 v3, v5, v3
; GFX9-NEXT: v_sub_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_sub_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fsub_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_sub_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_sub_f32_e32 v5, v7, v6
; GFX10-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_sub_f32_e32 v2, v7, v6
; GFX10-NEXT: v_sub_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fsub_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_sub_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_sub_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_sub_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_sub_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_sub_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_dual_sub_f32 v4, v5, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_sub_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_sub_f32_e32 v5, v7, v6
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fsub <4 x bfloat> %a, %b
ret <4 x bfloat> %op
@@ -11068,83 +10985,52 @@ define <3 x bfloat> @v_fmul_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX8-LABEL: v_fmul_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmul_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v3, v4, v3
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmul_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_mul_f32_e32 v4, v5, v4
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_f32_e32 v2, v7, v6
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fmul_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_mul_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <3 x bfloat> %a, %b
ret <3 x bfloat> %op
}
@@ -11195,82 +11081,81 @@ define <4 x bfloat> @v_fmul_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX8-LABEL: v_fmul_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_mul_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmul_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmul_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_mul_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_mul_f32_e32 v5, v7, v6
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_mul_f32_e32 v2, v7, v6
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fmul_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_mul_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_dual_mul_f32 v4, v5, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v7, v6
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <4 x bfloat> %a, %b
ret <4 x bfloat> %op
@@ -11354,138 +11239,138 @@ define <8 x bfloat> @v_fmul_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX8-LABEL: v_fmul_v8bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_mul_f32_e32 v0, v0, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_mul_f32_e32 v7, v9, v7
+; GFX8-NEXT: v_mul_f32_e32 v2, v2, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_mul_f32_e32 v6, v9, v6
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v5
-; GFX8-NEXT: v_mul_f32_e32 v4, v8, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_mul_f32_e32 v2, v2, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX8-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v5, v9, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v5, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v7, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmul_v8bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_mul_f32_e32 v7, v9, v7
+; GFX9-NEXT: v_mul_f32_e32 v2, v2, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_mul_f32_e32 v6, v9, v6
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_mul_f32_e32 v5, v9, v5
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v4, v8, v4
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v5
-; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, v2, v5
-; GFX9-NEXT: v_perm_b32 v2, v2, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX9-NEXT: v_mul_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, v3, v5
-; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v5, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v7, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmul_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_mul_f32_e32 v8, v9, v8
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_mul_f32_e32 v9, v11, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_mul_f32_e32 v8, v9, v8
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_mul_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_mul_f32_e32 v4, v11, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_mul_f32_e32 v10, v11, v10
+; GFX10-NEXT: v_mul_f32_e32 v11, v13, v12
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_mul_f32_e32 v5, v10, v9
; GFX10-NEXT: v_mul_f32_e32 v2, v2, v6
-; GFX10-NEXT: v_mul_f32_e32 v6, v12, v11
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v7
-; GFX10-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fmul_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_mul_f32 v9, v11, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v1, v1, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_mul_f32_e32 v4, v11, v10
-; GFX11-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_mul_f32_e32 v5, v10, v9
-; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT: v_mul_f32_e32 v2, v2, v6
-; GFX11-NEXT: v_mul_f32_e32 v6, v12, v11
+; GFX11-NEXT: v_dual_mul_f32 v1, v1, v5 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v2, v2, v6 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_mul_f32_e32 v3, v3, v7
-; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX11-NEXT: v_dual_mul_f32 v10, v11, v10 :: v_dual_mul_f32 v11, v13, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <8 x bfloat> %a, %b
ret <8 x bfloat> %op
@@ -11637,252 +11522,254 @@ define <16 x bfloat> @v_fmul_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX8-LABEL: v_fmul_v16bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_mul_f32_e32 v0, v0, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v7, v7, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_mul_f32_e32 v15, v17, v15
+; GFX8-NEXT: v_mul_f32_e32 v6, v6, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_mul_f32_e32 v14, v17, v14
+; GFX8-NEXT: v_mul_f32_e32 v5, v5, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_mul_f32_e32 v13, v17, v13
+; GFX8-NEXT: v_mul_f32_e32 v4, v4, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_mul_f32_e32 v12, v17, v12
+; GFX8-NEXT: v_mul_f32_e32 v3, v3, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_mul_f32_e32 v11, v17, v11
+; GFX8-NEXT: v_mul_f32_e32 v2, v2, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_mul_f32_e32 v10, v17, v10
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v9
-; GFX8-NEXT: v_mul_f32_e32 v8, v16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_mul_f32_e32 v2, v2, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, v3, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_mul_f32_e32 v4, v4, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_mul_f32_e32 v5, v5, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_mul_f32_e32 v6, v6, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX8-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_mul_f32_e32 v7, v7, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, v0, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v8, 16
-; GFX8-NEXT: s_setpc_b64 s[30:31]
-;
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v9, v17, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v9, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v10, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v11, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v12, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v13, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v14, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v15, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
; GFX9-LABEL: v_fmul_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_mul_f32_e32 v7, v7, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_mul_f32_e32 v15, v17, v15
+; GFX9-NEXT: v_mul_f32_e32 v6, v6, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_mul_f32_e32 v14, v17, v14
+; GFX9-NEXT: v_mul_f32_e32 v5, v5, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_mul_f32_e32 v13, v17, v13
+; GFX9-NEXT: v_mul_f32_e32 v4, v4, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_mul_f32_e32 v12, v17, v12
+; GFX9-NEXT: v_mul_f32_e32 v3, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_mul_f32_e32 v11, v17, v11
+; GFX9-NEXT: v_mul_f32_e32 v2, v2, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_mul_f32_e32 v10, v17, v10
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v8
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v0
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_mul_f32_e32 v9, v17, v9
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v8
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v8, v16, v8
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v9
-; GFX9-NEXT: v_perm_b32 v1, v1, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, v2, v9
-; GFX9-NEXT: v_perm_b32 v2, v2, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, v3, v9
-; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_mul_f32_e32 v4, v4, v9
-; GFX9-NEXT: v_perm_b32 v4, v4, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, v5, v9
-; GFX9-NEXT: v_perm_b32 v5, v5, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_mul_f32_e32 v6, v6, v9
-; GFX9-NEXT: v_perm_b32 v6, v6, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX9-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_mul_f32_e32 v7, v7, v9
-; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v9, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v11, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v13, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmul_v16bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v5
; GFX10-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX10-NEXT: v_mul_f32_e32 v7, v7, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX10-NEXT: v_mul_f32_e32 v15, v17, v15
+; GFX10-NEXT: v_mul_f32_e32 v6, v6, v14
+; GFX10-NEXT: v_mul_f32_e32 v14, v19, v18
+; GFX10-NEXT: v_mul_f32_e32 v5, v5, v13
+; GFX10-NEXT: v_mul_f32_e32 v13, v21, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_mul_f32_e32 v17, v18, v17
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_mul_f32_e32 v18, v20, v19
; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX10-NEXT: v_mul_f32_e32 v19, v20, v19
+; GFX10-NEXT: v_mul_f32_e32 v20, v22, v21
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v8
-; GFX10-NEXT: v_mul_f32_e32 v8, v18, v17
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v9
-; GFX10-NEXT: v_mul_f32_e32 v9, v20, v19
; GFX10-NEXT: v_mul_f32_e32 v2, v2, v10
-; GFX10-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11
-; GFX10-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX10-NEXT: v_mul_f32_e32 v8, v9, v8
-; GFX10-NEXT: v_mul_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_mul_f32_e32 v9, v16, v11
+; GFX10-NEXT: v_mul_f32_e32 v3, v3, v11
; GFX10-NEXT: v_mul_f32_e32 v4, v4, v12
-; GFX10-NEXT: v_mul_f32_e32 v10, v18, v17
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_mul_f32_e32 v5, v5, v11
-; GFX10-NEXT: v_mul_f32_e32 v11, v13, v12
-; GFX10-NEXT: v_mul_f32_e32 v6, v6, v14
-; GFX10-NEXT: v_mul_f32_e32 v12, v17, v16
-; GFX10-NEXT: v_mul_f32_e32 v7, v7, v15
-; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX10-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fmul_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mul_f32_e32 v2, v2, v10
-; GFX11-NEXT: v_dual_mul_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v1, v1, v9 :: v_dual_and_b32 v10, 0xffff0000, v11
-; GFX11-NEXT: v_mul_f32_e32 v9, v20, v19
-; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v3, v3, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v8
-; GFX11-NEXT: v_mul_f32_e32 v8, v18, v17
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_dual_mul_f32 v10, v18, v17 :: v_dual_lshlrev_b32 v17, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_mul_f32 v4, v4, v12 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_dual_mul_f32 v8, v9, v8 :: v_dual_mul_f32 v9, v16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v4, v4, v12 :: v_dual_and_b32 v5, 0xffff0000, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: v_mul_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_mul_f32_e32 v13, v21, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_dual_mul_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: v_mul_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11-NEXT: v_mul_f32_e32 v5, v5, v11
-; GFX11-NEXT: v_mul_f32_e32 v11, v13, v12
-; GFX11-NEXT: v_mul_f32_e32 v12, v17, v16
-; GFX11-NEXT: v_dual_mul_f32 v6, v6, v14 :: v_dual_mul_f32 v7, v7, v15
-; GFX11-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-NEXT: v_mul_f32_e32 v15, v17, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v6, v6, v14 :: v_dual_lshlrev_b32 v17, 16, v11
+; GFX11-NEXT: v_mul_f32_e32 v14, v19, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_mul_f32 v17, v18, v17 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-NEXT: v_mul_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_dual_mul_f32 v18, v20, v19 :: v_dual_lshlrev_b32 v19, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_dual_mul_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v19, v20, v19 :: v_dual_mul_f32 v20, v22, v21
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <16 x bfloat> %a, %b
ret <16 x bfloat> %op
@@ -12290,483 +12177,480 @@ define <32 x bfloat> @v_fmul_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX8-LABEL: v_fmul_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX8-NEXT: v_mul_f32_e32 v31, v32, v31
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v30, v14, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_mul_f32_e32 v14, v32, v14
+; GFX8-NEXT: v_mul_f32_e32 v13, v13, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_mul_f32_e32 v29, v32, v29
+; GFX8-NEXT: v_mul_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_mul_f32_e32 v28, v32, v28
+; GFX8-NEXT: v_mul_f32_e32 v11, v11, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_mul_f32_e32 v27, v32, v27
+; GFX8-NEXT: v_mul_f32_e32 v10, v10, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX8-NEXT: v_mul_f32_e32 v26, v32, v26
+; GFX8-NEXT: v_mul_f32_e32 v9, v9, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_mul_f32_e32 v8, v8, v24
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX8-NEXT: v_mul_f32_e32 v25, v32, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16
+; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16
+; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16
+; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16
+; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16
+; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_mul_f32_e32 v32, v32, v33
+; GFX8-NEXT: v_mul_f32_e32 v15, v15, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_mul_f32_e32 v24, v33, v24
+; GFX8-NEXT: v_mul_f32_e32 v7, v7, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_mul_f32_e32 v23, v33, v23
+; GFX8-NEXT: v_mul_f32_e32 v6, v6, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_mul_f32_e32 v22, v33, v22
+; GFX8-NEXT: v_mul_f32_e32 v5, v5, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_mul_f32_e32 v21, v33, v21
+; GFX8-NEXT: v_mul_f32_e32 v4, v4, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_mul_f32_e32 v20, v33, v20
+; GFX8-NEXT: v_mul_f32_e32 v3, v3, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_mul_f32_e32 v19, v33, v19
+; GFX8-NEXT: v_mul_f32_e32 v2, v2, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_mul_f32_e32 v18, v33, v18
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v17
-; GFX8-NEXT: v_mul_f32_e32 v16, v31, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_mul_f32_e32 v17, v33, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_mul_f32_e32 v2, v2, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_mul_f32_e32 v3, v3, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX8-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_mul_f32_e32 v4, v4, v17
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_mul_f32_e32 v5, v5, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_mul_f32_e32 v6, v6, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_mul_f32_e32 v7, v7, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_mul_f32_e32 v8, v8, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX8-NEXT: v_mul_f32_e32 v9, v9, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
-; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX8-NEXT: v_mul_f32_e32 v10, v10, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27
-; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX8-NEXT: v_mul_f32_e32 v11, v11, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
-; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX8-NEXT: v_mul_f32_e32 v12, v12, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29
-; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX8-NEXT: v_mul_f32_e32 v13, v13, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX8-NEXT: v_mul_f32_e32 v14, v14, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX8-NEXT: v_mul_f32_e32 v15, v15, v17
-; GFX8-NEXT: v_mul_f32_e32 v16, v18, v16
; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16
+; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16
+; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmul_v32bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX9-NEXT: v_mul_f32_e32 v31, v32, v31
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_mul_f32_e32 v14, v14, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_mul_f32_e32 v30, v32, v30
+; GFX9-NEXT: v_mul_f32_e32 v13, v13, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_mul_f32_e32 v29, v32, v29
+; GFX9-NEXT: v_mul_f32_e32 v12, v12, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_mul_f32_e32 v28, v32, v28
+; GFX9-NEXT: v_mul_f32_e32 v11, v11, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_mul_f32_e32 v27, v32, v27
+; GFX9-NEXT: v_mul_f32_e32 v10, v10, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_mul_f32_e32 v26, v32, v26
+; GFX9-NEXT: v_mul_f32_e32 v9, v9, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX9-NEXT: v_mul_f32_e32 v8, v8, v24
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX9-NEXT: v_mul_f32_e32 v25, v32, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4
+; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4
+; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4
+; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4
+; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_mul_f32_e32 v32, v32, v33
+; GFX9-NEXT: v_mul_f32_e32 v15, v15, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_mul_f32_e32 v24, v33, v24
+; GFX9-NEXT: v_mul_f32_e32 v7, v7, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_mul_f32_e32 v23, v33, v23
+; GFX9-NEXT: v_mul_f32_e32 v6, v6, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_mul_f32_e32 v22, v33, v22
+; GFX9-NEXT: v_mul_f32_e32 v5, v5, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_mul_f32_e32 v21, v33, v21
+; GFX9-NEXT: v_mul_f32_e32 v4, v4, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_mul_f32_e32 v20, v33, v20
+; GFX9-NEXT: v_mul_f32_e32 v3, v3, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_mul_f32_e32 v19, v33, v19
+; GFX9-NEXT: v_mul_f32_e32 v2, v2, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v16, v31, v16
+; GFX9-NEXT: v_mul_f32_e32 v18, v33, v18
; GFX9-NEXT: v_mul_f32_e32 v1, v1, v17
-; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_mul_f32_e32 v2, v2, v17
-; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_mul_f32_e32 v3, v3, v17
-; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_mul_f32_e32 v4, v4, v17
-; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_mul_f32_e32 v5, v5, v17
-; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_mul_f32_e32 v6, v6, v17
-; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_mul_f32_e32 v7, v7, v17
-; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24
-; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX9-NEXT: v_mul_f32_e32 v8, v8, v17
-; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_mul_f32_e32 v9, v9, v17
-; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26
-; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX9-NEXT: v_mul_f32_e32 v10, v10, v17
-; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27
-; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX9-NEXT: v_mul_f32_e32 v11, v11, v17
-; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28
-; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX9-NEXT: v_mul_f32_e32 v12, v12, v17
-; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29
-; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX9-NEXT: v_mul_f32_e32 v13, v13, v17
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30
-; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX9-NEXT: v_mul_f32_e32 v14, v14, v17
-; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX9-NEXT: v_mul_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX9-NEXT: v_mul_f32_e32 v15, v15, v17
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_mul_f32_e32 v17, v33, v17
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmul_v32bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_mul_f32_e32 v39, v48, v39
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17
+; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21
-; GFX10-NEXT: v_mul_f32_e32 v21, v53, v52
-; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22
-; GFX10-NEXT: v_mul_f32_e32 v22, v55, v54
-; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9
+; GFX10-NEXT: v_mul_f32_e32 v49, v50, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16
+; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9
; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX10-NEXT: v_mul_f32_e32 v32, v33, v32
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10
-; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_mul_f32_e32 v33, v34, v33
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20
+; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_mul_f32_e32 v35, v36, v35
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3
+; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_mul_f32_e32 v37, v38, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18
+; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX10-NEXT: v_mul_f32_e32 v34, v35, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28
-; GFX10-NEXT: v_mul_f32_e32 v36, v37, v36
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12
-; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_mul_f32_e32 v51, v52, v51
+; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25
+; GFX10-NEXT: v_mul_f32_e32 v25, v54, v53
+; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24
+; GFX10-NEXT: v_mul_f32_e32 v24, v64, v55
+; GFX10-NEXT: v_mul_f32_e32 v7, v7, v23
+; GFX10-NEXT: v_mul_f32_e32 v23, v66, v65
+; GFX10-NEXT: v_mul_f32_e32 v6, v6, v22
+; GFX10-NEXT: v_mul_f32_e32 v22, v68, v67
+; GFX10-NEXT: v_mul_f32_e32 v5, v5, v21
+; GFX10-NEXT: v_mul_f32_e32 v21, v30, v34
+; GFX10-NEXT: v_mul_f32_e32 v29, v29, v36
+; GFX10-NEXT: v_mul_f32_e32 v28, v28, v38
+; GFX10-NEXT: v_mul_f32_e32 v27, v27, v48
+; GFX10-NEXT: v_mul_f32_e32 v26, v26, v50
; GFX10-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; GFX10-NEXT: v_mul_f32_e32 v38, v39, v38
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13
-; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX10-NEXT: v_mul_f32_e32 v3, v3, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30
-; GFX10-NEXT: v_mul_f32_e32 v48, v49, v48
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14
-; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX10-NEXT: v_mul_f32_e32 v4, v4, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX10-NEXT: v_mul_f32_e32 v50, v51, v50
-; GFX10-NEXT: v_mul_f32_e32 v23, v65, v64
-; GFX10-NEXT: v_mul_f32_e32 v8, v8, v24
-; GFX10-NEXT: v_mul_f32_e32 v24, v67, v66
-; GFX10-NEXT: v_mul_f32_e32 v9, v9, v25
-; GFX10-NEXT: v_mul_f32_e32 v25, v33, v68
-; GFX10-NEXT: v_mul_f32_e32 v10, v10, v26
-; GFX10-NEXT: v_mul_f32_e32 v16, v35, v16
-; GFX10-NEXT: v_mul_f32_e32 v11, v11, v27
-; GFX10-NEXT: v_mul_f32_e32 v17, v37, v17
-; GFX10-NEXT: v_mul_f32_e32 v12, v12, v28
-; GFX10-NEXT: v_mul_f32_e32 v18, v39, v18
-; GFX10-NEXT: v_mul_f32_e32 v13, v13, v29
-; GFX10-NEXT: v_mul_f32_e32 v19, v49, v19
-; GFX10-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302
-; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302
-; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302
+; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302
+; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302
+; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302
+; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302
+; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31
-; GFX10-NEXT: v_mul_f32_e32 v20, v20, v21
-; GFX10-NEXT: v_mul_f32_e32 v15, v15, v22
-; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX10-NEXT: v_mul_f32_e32 v16, v32, v16
+; GFX10-NEXT: v_mul_f32_e32 v15, v15, v17
+; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fmul_v32bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10
-; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX11-NEXT: v_dual_mul_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28
-; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10
+; GFX11-NEXT: v_dual_mul_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_dual_mul_f32 v2, v2, v18 :: v_dual_mul_f32 v3, v3, v19
+; GFX11-NEXT: v_dual_mul_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26
+; GFX11-NEXT: v_dual_mul_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_mul_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_dual_mul_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28
; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mul_f32_e32 v10, v10, v26
+; GFX11-NEXT: v_mul_f32_e32 v26, v52, v51
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_mul_f32_e32 v25, v54, v53
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30
-; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_dual_mul_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4
-; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_mul_f32_e32 v4, v4, v20
-; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_mul_f32 v9, v9, v25
-; GFX11-NEXT: v_mul_f32_e32 v25, v69, v68
-; GFX11-NEXT: v_dual_mul_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3
-; GFX11-NEXT: v_mul_f32_e32 v27, v81, v80
-; GFX11-NEXT: v_mul_f32_e32 v12, v12, v28
-; GFX11-NEXT: v_dual_mul_f32 v28, v83, v82 :: v_dual_mul_f32 v29, v85, v84
-; GFX11-NEXT: v_dual_mul_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_mul_f32_e32 v22, v55, v54
-; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_dual_mul_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_mul_f32_e32 v24, v64, v55
+; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_mul_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_mul_f32_e32 v23, v66, v65
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_mul_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_dual_mul_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_mul_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-NEXT: v_dual_mul_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_mul_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: v_mul_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_mul_f32_e32 v37, v86, v85
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11-NEXT: v_mul_f32_e32 v14, v14, v30
-; GFX11-NEXT: v_dual_mul_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_mul_f32_e32 v23, v65, v64
-; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT: v_dual_mul_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21
-; GFX11-NEXT: v_mul_f32_e32 v2, v2, v18
-; GFX11-NEXT: v_dual_mul_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16
-; GFX11-NEXT: v_mul_f32_e32 v18, v39, v38
-; GFX11-NEXT: v_dual_mul_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16
-; GFX11-NEXT: v_mul_f32_e32 v19, v49, v48
-; GFX11-NEXT: v_mul_f32_e32 v17, v37, v36
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX11-NEXT: v_dual_mul_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_mul_f32_e32 v21, v53, v52
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v16
-; GFX11-NEXT: v_mul_f32_e32 v16, v35, v34
-; GFX11-NEXT: v_mul_f32_e32 v32, v33, v32
-; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302
-; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302
-; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302
-; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mul_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31
-; GFX11-NEXT: v_mul_f32_e32 v15, v15, v17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mul_f32 v30, v36, v35 :: v_dual_mul_f32 v33, v34, v33
+; GFX11-NEXT: v_dual_mul_f32 v34, v80, v71 :: v_dual_mul_f32 v35, v82, v81
+; GFX11-NEXT: v_mul_f32_e32 v36, v84, v83
+; GFX11-NEXT: v_dual_mul_f32 v16, v32, v16 :: v_dual_mul_f32 v15, v15, v17
+; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fmul <32 x bfloat> %a, %b
@@ -13396,83 +13280,52 @@ define <3 x bfloat> @v_minnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX8-LABEL: v_minnum_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_min_f32_e32 v3, v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_min_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_minnum_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_min_f32_e32 v3, v4, v3
; GFX9-NEXT: v_min_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_min_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minnum_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_min_f32_e32 v4, v5, v4
; GFX10-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_min_f32_e32 v2, v7, v6
; GFX10-NEXT: v_min_f32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_minnum_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_min_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <3 x bfloat> @llvm.minnum.v3bf16(<3 x bfloat> %a, <3 x bfloat> %b)
ret <3 x bfloat> %op
}
@@ -13539,82 +13392,81 @@ define <4 x bfloat> @v_minnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX8-LABEL: v_minnum_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_min_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_min_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_minnum_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_min_f32_e32 v3, v5, v3
; GFX9-NEXT: v_min_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_min_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minnum_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_min_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_min_f32_e32 v5, v7, v6
; GFX10-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_min_f32_e32 v2, v7, v6
; GFX10-NEXT: v_min_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minnum_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_min_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_min_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_dual_min_f32 v4, v5, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_min_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_min_f32_e32 v5, v7, v6
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.minnum.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <4 x bfloat> %op
@@ -13730,138 +13582,138 @@ define <8 x bfloat> @v_minnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX8-LABEL: v_minnum_v8bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX8-NEXT: v_min_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_min_f32_e32 v7, v9, v7
+; GFX8-NEXT: v_min_f32_e32 v2, v2, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_min_f32_e32 v6, v9, v6
; GFX8-NEXT: v_min_f32_e32 v1, v1, v5
-; GFX8-NEXT: v_min_f32_e32 v4, v8, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX8-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_min_f32_e32 v3, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_min_f32_e32 v5, v9, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v5, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v7, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_minnum_v8bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_min_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_min_f32_e32 v7, v9, v7
+; GFX9-NEXT: v_min_f32_e32 v2, v2, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_min_f32_e32 v4, v8, v4
+; GFX9-NEXT: v_min_f32_e32 v6, v9, v6
; GFX9-NEXT: v_min_f32_e32 v1, v1, v5
-; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_min_f32_e32 v2, v2, v5
-; GFX9-NEXT: v_perm_b32 v2, v2, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX9-NEXT: v_min_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_min_f32_e32 v3, v3, v5
-; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_min_f32_e32 v5, v9, v5
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_perm_b32 v0, v0, v5, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v7, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minnum_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_min_f32_e32 v8, v9, v8
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_min_f32_e32 v9, v11, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_min_f32_e32 v8, v9, v8
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_min_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_min_f32_e32 v4, v11, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_min_f32_e32 v10, v11, v10
+; GFX10-NEXT: v_min_f32_e32 v11, v13, v12
+; GFX10-NEXT: v_min_f32_e32 v0, v0, v4
; GFX10-NEXT: v_min_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_min_f32_e32 v5, v10, v9
; GFX10-NEXT: v_min_f32_e32 v2, v2, v6
-; GFX10-NEXT: v_min_f32_e32 v6, v12, v11
; GFX10-NEXT: v_min_f32_e32 v3, v3, v7
-; GFX10-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minnum_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_min_f32 v9, v11, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_min_f32_e32 v0, v0, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v1, v1, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_min_f32_e32 v4, v11, v10
-; GFX11-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_min_f32_e32 v5, v10, v9
-; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT: v_min_f32_e32 v2, v2, v6
-; GFX11-NEXT: v_min_f32_e32 v6, v12, v11
+; GFX11-NEXT: v_dual_min_f32 v1, v1, v5 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_min_f32 v2, v2, v6 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_min_f32_e32 v3, v3, v7
-; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX11-NEXT: v_dual_min_f32 v10, v11, v10 :: v_dual_min_f32 v11, v13, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <8 x bfloat> @llvm.minnum.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <8 x bfloat> %op
@@ -14077,252 +13929,254 @@ define <16 x bfloat> @v_minnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX8-LABEL: v_minnum_v16bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_min_f32_e32 v0, v0, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX8-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v1
+; GFX8-NEXT: v_min_f32_e32 v7, v7, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_min_f32_e32 v15, v17, v15
+; GFX8-NEXT: v_min_f32_e32 v6, v6, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_min_f32_e32 v14, v17, v14
+; GFX8-NEXT: v_min_f32_e32 v5, v5, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_min_f32_e32 v13, v17, v13
+; GFX8-NEXT: v_min_f32_e32 v4, v4, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_min_f32_e32 v12, v17, v12
+; GFX8-NEXT: v_min_f32_e32 v3, v3, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_min_f32_e32 v11, v17, v11
+; GFX8-NEXT: v_min_f32_e32 v2, v2, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_min_f32_e32 v10, v17, v10
; GFX8-NEXT: v_min_f32_e32 v1, v1, v9
-; GFX8-NEXT: v_min_f32_e32 v8, v16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_min_f32_e32 v2, v2, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_min_f32_e32 v3, v3, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_min_f32_e32 v4, v4, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_min_f32_e32 v5, v5, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_min_f32_e32 v6, v6, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX8-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_min_f32_e32 v7, v7, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_min_f32_e32 v9, v17, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v9, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v10, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v11, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v12, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v13, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v14, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v15, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_minnum_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_min_f32_e32 v7, v7, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_min_f32_e32 v15, v17, v15
+; GFX9-NEXT: v_min_f32_e32 v6, v6, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_min_f32_e32 v14, v17, v14
+; GFX9-NEXT: v_min_f32_e32 v5, v5, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_min_f32_e32 v13, v17, v13
+; GFX9-NEXT: v_min_f32_e32 v4, v4, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_min_f32_e32 v12, v17, v12
+; GFX9-NEXT: v_min_f32_e32 v3, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_min_f32_e32 v11, v17, v11
+; GFX9-NEXT: v_min_f32_e32 v2, v2, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_min_f32_e32 v10, v17, v10
+; GFX9-NEXT: v_min_f32_e32 v1, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v8
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v0
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_min_f32_e32 v9, v17, v9
; GFX9-NEXT: v_min_f32_e32 v0, v0, v8
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_min_f32_e32 v8, v16, v8
-; GFX9-NEXT: v_min_f32_e32 v1, v1, v9
-; GFX9-NEXT: v_perm_b32 v1, v1, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_min_f32_e32 v2, v2, v9
-; GFX9-NEXT: v_perm_b32 v2, v2, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_min_f32_e32 v3, v3, v9
-; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_min_f32_e32 v4, v4, v9
-; GFX9-NEXT: v_perm_b32 v4, v4, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_min_f32_e32 v5, v5, v9
-; GFX9-NEXT: v_perm_b32 v5, v5, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_min_f32_e32 v6, v6, v9
-; GFX9-NEXT: v_perm_b32 v6, v6, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX9-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_min_f32_e32 v7, v7, v9
-; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v9, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v11, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v13, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minnum_v16bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v5
; GFX10-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX10-NEXT: v_min_f32_e32 v7, v7, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX10-NEXT: v_min_f32_e32 v15, v17, v15
+; GFX10-NEXT: v_min_f32_e32 v6, v6, v14
+; GFX10-NEXT: v_min_f32_e32 v14, v19, v18
+; GFX10-NEXT: v_min_f32_e32 v5, v5, v13
+; GFX10-NEXT: v_min_f32_e32 v13, v21, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_min_f32_e32 v17, v18, v17
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_min_f32_e32 v18, v20, v19
; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX10-NEXT: v_min_f32_e32 v19, v20, v19
+; GFX10-NEXT: v_min_f32_e32 v20, v22, v21
; GFX10-NEXT: v_min_f32_e32 v0, v0, v8
-; GFX10-NEXT: v_min_f32_e32 v8, v18, v17
; GFX10-NEXT: v_min_f32_e32 v1, v1, v9
-; GFX10-NEXT: v_min_f32_e32 v9, v20, v19
; GFX10-NEXT: v_min_f32_e32 v2, v2, v10
-; GFX10-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11
-; GFX10-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX10-NEXT: v_min_f32_e32 v8, v9, v8
-; GFX10-NEXT: v_min_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_min_f32_e32 v9, v16, v11
+; GFX10-NEXT: v_min_f32_e32 v3, v3, v11
; GFX10-NEXT: v_min_f32_e32 v4, v4, v12
-; GFX10-NEXT: v_min_f32_e32 v10, v18, v17
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_min_f32_e32 v5, v5, v11
-; GFX10-NEXT: v_min_f32_e32 v11, v13, v12
-; GFX10-NEXT: v_min_f32_e32 v6, v6, v14
-; GFX10-NEXT: v_min_f32_e32 v12, v17, v16
-; GFX10-NEXT: v_min_f32_e32 v7, v7, v15
-; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX10-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minnum_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_min_f32_e32 v2, v2, v10
-; GFX11-NEXT: v_dual_min_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v1, v1, v9 :: v_dual_and_b32 v10, 0xffff0000, v11
-; GFX11-NEXT: v_min_f32_e32 v9, v20, v19
-; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v3, v3, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v8
-; GFX11-NEXT: v_min_f32_e32 v8, v18, v17
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_dual_min_f32 v10, v18, v17 :: v_dual_lshlrev_b32 v17, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_min_f32 v4, v4, v12 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_dual_min_f32 v8, v9, v8 :: v_dual_min_f32 v9, v16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v4, v4, v12 :: v_dual_and_b32 v5, 0xffff0000, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: v_min_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_min_f32_e32 v13, v21, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_dual_min_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v0, v0, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: v_min_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11-NEXT: v_min_f32_e32 v5, v5, v11
-; GFX11-NEXT: v_min_f32_e32 v11, v13, v12
-; GFX11-NEXT: v_min_f32_e32 v12, v17, v16
-; GFX11-NEXT: v_dual_min_f32 v6, v6, v14 :: v_dual_min_f32 v7, v7, v15
-; GFX11-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-NEXT: v_min_f32_e32 v15, v17, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v6, v6, v14 :: v_dual_lshlrev_b32 v17, 16, v11
+; GFX11-NEXT: v_min_f32_e32 v14, v19, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_min_f32 v17, v18, v17 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-NEXT: v_min_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_dual_min_f32 v18, v20, v19 :: v_dual_lshlrev_b32 v19, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_dual_min_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_min_f32 v19, v20, v19 :: v_dual_min_f32 v20, v22, v21
+; GFX11-NEXT: v_min_f32_e32 v1, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <16 x bfloat> @llvm.minnum.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b)
ret <16 x bfloat> %op
@@ -14858,483 +14712,480 @@ define <32 x bfloat> @v_minnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX8-LABEL: v_minnum_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX8-NEXT: v_min_f32_e32 v31, v32, v31
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_min_f32_e32 v1, v1, v17
-; GFX8-NEXT: v_min_f32_e32 v16, v31, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX8-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_min_f32_e32 v2, v2, v17
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX8-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_min_f32_e32 v3, v3, v17
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX8-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_min_f32_e32 v4, v4, v17
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_min_f32_e32 v5, v5, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_min_f32_e32 v6, v6, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_min_f32_e32 v7, v7, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
+; GFX8-NEXT: v_min_f32_e32 v30, v14, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_min_f32_e32 v14, v32, v14
+; GFX8-NEXT: v_min_f32_e32 v13, v13, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_min_f32_e32 v29, v32, v29
+; GFX8-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_min_f32_e32 v28, v32, v28
+; GFX8-NEXT: v_min_f32_e32 v11, v11, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_min_f32_e32 v27, v32, v27
+; GFX8-NEXT: v_min_f32_e32 v10, v10, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX8-NEXT: v_min_f32_e32 v26, v32, v26
+; GFX8-NEXT: v_min_f32_e32 v9, v9, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_min_f32_e32 v8, v8, v18
+; GFX8-NEXT: v_min_f32_e32 v8, v8, v24
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX8-NEXT: v_min_f32_e32 v25, v32, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX8-NEXT: v_min_f32_e32 v9, v9, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
-; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX8-NEXT: v_min_f32_e32 v10, v10, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27
-; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX8-NEXT: v_min_f32_e32 v11, v11, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
-; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX8-NEXT: v_min_f32_e32 v12, v12, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29
-; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX8-NEXT: v_min_f32_e32 v13, v13, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX8-NEXT: v_min_f32_e32 v14, v14, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16
+; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16
+; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16
+; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16
+; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16
+; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_min_f32_e32 v32, v32, v33
+; GFX8-NEXT: v_min_f32_e32 v15, v15, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_min_f32_e32 v24, v33, v24
+; GFX8-NEXT: v_min_f32_e32 v7, v7, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_min_f32_e32 v23, v33, v23
+; GFX8-NEXT: v_min_f32_e32 v6, v6, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_min_f32_e32 v22, v33, v22
+; GFX8-NEXT: v_min_f32_e32 v5, v5, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_min_f32_e32 v21, v33, v21
+; GFX8-NEXT: v_min_f32_e32 v4, v4, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_min_f32_e32 v20, v33, v20
+; GFX8-NEXT: v_min_f32_e32 v3, v3, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_min_f32_e32 v19, v33, v19
+; GFX8-NEXT: v_min_f32_e32 v2, v2, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX8-NEXT: v_min_f32_e32 v15, v15, v17
-; GFX8-NEXT: v_min_f32_e32 v16, v18, v16
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_min_f32_e32 v18, v33, v18
+; GFX8-NEXT: v_min_f32_e32 v1, v1, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_min_f32_e32 v17, v33, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16
+; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16
+; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_minnum_v32bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX9-NEXT: v_min_f32_e32 v31, v32, v31
-; GFX9-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_min_f32_e32 v14, v14, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_min_f32_e32 v30, v32, v30
+; GFX9-NEXT: v_min_f32_e32 v13, v13, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_min_f32_e32 v29, v32, v29
+; GFX9-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_min_f32_e32 v28, v32, v28
+; GFX9-NEXT: v_min_f32_e32 v11, v11, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_min_f32_e32 v27, v32, v27
+; GFX9-NEXT: v_min_f32_e32 v10, v10, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_min_f32_e32 v26, v32, v26
+; GFX9-NEXT: v_min_f32_e32 v9, v9, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX9-NEXT: v_min_f32_e32 v8, v8, v24
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX9-NEXT: v_min_f32_e32 v25, v32, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4
+; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4
+; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4
+; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4
+; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_min_f32_e32 v32, v32, v33
+; GFX9-NEXT: v_min_f32_e32 v15, v15, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_min_f32_e32 v24, v33, v24
+; GFX9-NEXT: v_min_f32_e32 v7, v7, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_min_f32_e32 v23, v33, v23
+; GFX9-NEXT: v_min_f32_e32 v6, v6, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_min_f32_e32 v22, v33, v22
+; GFX9-NEXT: v_min_f32_e32 v5, v5, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_min_f32_e32 v21, v33, v21
+; GFX9-NEXT: v_min_f32_e32 v4, v4, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_min_f32_e32 v20, v33, v20
+; GFX9-NEXT: v_min_f32_e32 v3, v3, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_min_f32_e32 v19, v33, v19
+; GFX9-NEXT: v_min_f32_e32 v2, v2, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_min_f32_e32 v16, v31, v16
+; GFX9-NEXT: v_min_f32_e32 v18, v33, v18
; GFX9-NEXT: v_min_f32_e32 v1, v1, v17
-; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_min_f32_e32 v2, v2, v17
-; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_min_f32_e32 v3, v3, v17
-; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_min_f32_e32 v4, v4, v17
-; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_min_f32_e32 v5, v5, v17
-; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_min_f32_e32 v6, v6, v17
-; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_min_f32_e32 v7, v7, v17
-; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24
-; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX9-NEXT: v_min_f32_e32 v8, v8, v17
-; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_min_f32_e32 v9, v9, v17
-; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26
-; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX9-NEXT: v_min_f32_e32 v10, v10, v17
-; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27
-; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX9-NEXT: v_min_f32_e32 v11, v11, v17
-; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28
-; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX9-NEXT: v_min_f32_e32 v12, v12, v17
-; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29
-; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX9-NEXT: v_min_f32_e32 v13, v13, v17
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30
-; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX9-NEXT: v_min_f32_e32 v14, v14, v17
-; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX9-NEXT: v_min_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX9-NEXT: v_min_f32_e32 v15, v15, v17
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_min_f32_e32 v17, v33, v17
+; GFX9-NEXT: v_min_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_minnum_v32bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_min_f32_e32 v39, v48, v39
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17
+; GFX10-NEXT: v_min_f32_e32 v11, v11, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_min_f32_e32 v5, v5, v21
-; GFX10-NEXT: v_min_f32_e32 v21, v53, v52
-; GFX10-NEXT: v_min_f32_e32 v6, v6, v22
-; GFX10-NEXT: v_min_f32_e32 v22, v55, v54
-; GFX10-NEXT: v_min_f32_e32 v7, v7, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9
+; GFX10-NEXT: v_min_f32_e32 v49, v50, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16
+; GFX10-NEXT: v_min_f32_e32 v10, v10, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9
; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX10-NEXT: v_min_f32_e32 v32, v33, v32
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10
-; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_min_f32_e32 v33, v34, v33
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20
+; GFX10-NEXT: v_min_f32_e32 v14, v14, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_min_f32_e32 v35, v36, v35
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX10-NEXT: v_min_f32_e32 v13, v13, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3
+; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_min_f32_e32 v37, v38, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18
+; GFX10-NEXT: v_min_f32_e32 v12, v12, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX10-NEXT: v_min_f32_e32 v34, v35, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX10-NEXT: v_min_f32_e32 v1, v1, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28
-; GFX10-NEXT: v_min_f32_e32 v36, v37, v36
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12
-; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_min_f32_e32 v51, v52, v51
+; GFX10-NEXT: v_min_f32_e32 v9, v9, v25
+; GFX10-NEXT: v_min_f32_e32 v25, v54, v53
+; GFX10-NEXT: v_min_f32_e32 v8, v8, v24
+; GFX10-NEXT: v_min_f32_e32 v24, v64, v55
+; GFX10-NEXT: v_min_f32_e32 v7, v7, v23
+; GFX10-NEXT: v_min_f32_e32 v23, v66, v65
+; GFX10-NEXT: v_min_f32_e32 v6, v6, v22
+; GFX10-NEXT: v_min_f32_e32 v22, v68, v67
+; GFX10-NEXT: v_min_f32_e32 v5, v5, v21
+; GFX10-NEXT: v_min_f32_e32 v21, v30, v34
+; GFX10-NEXT: v_min_f32_e32 v29, v29, v36
+; GFX10-NEXT: v_min_f32_e32 v28, v28, v38
+; GFX10-NEXT: v_min_f32_e32 v27, v27, v48
+; GFX10-NEXT: v_min_f32_e32 v26, v26, v50
; GFX10-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; GFX10-NEXT: v_min_f32_e32 v38, v39, v38
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13
-; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX10-NEXT: v_min_f32_e32 v3, v3, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30
-; GFX10-NEXT: v_min_f32_e32 v48, v49, v48
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14
-; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX10-NEXT: v_min_f32_e32 v4, v4, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX10-NEXT: v_min_f32_e32 v50, v51, v50
-; GFX10-NEXT: v_min_f32_e32 v23, v65, v64
-; GFX10-NEXT: v_min_f32_e32 v8, v8, v24
-; GFX10-NEXT: v_min_f32_e32 v24, v67, v66
-; GFX10-NEXT: v_min_f32_e32 v9, v9, v25
-; GFX10-NEXT: v_min_f32_e32 v25, v33, v68
-; GFX10-NEXT: v_min_f32_e32 v10, v10, v26
-; GFX10-NEXT: v_min_f32_e32 v16, v35, v16
-; GFX10-NEXT: v_min_f32_e32 v11, v11, v27
-; GFX10-NEXT: v_min_f32_e32 v17, v37, v17
-; GFX10-NEXT: v_min_f32_e32 v12, v12, v28
-; GFX10-NEXT: v_min_f32_e32 v18, v39, v18
-; GFX10-NEXT: v_min_f32_e32 v13, v13, v29
-; GFX10-NEXT: v_min_f32_e32 v19, v49, v19
-; GFX10-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302
-; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302
-; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302
+; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302
+; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302
+; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302
+; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302
+; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31
-; GFX10-NEXT: v_min_f32_e32 v20, v20, v21
-; GFX10-NEXT: v_min_f32_e32 v15, v15, v22
-; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX10-NEXT: v_min_f32_e32 v16, v32, v16
+; GFX10-NEXT: v_min_f32_e32 v15, v15, v17
+; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_minnum_v32bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10
-; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX11-NEXT: v_dual_min_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_dual_min_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28
-; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10
+; GFX11-NEXT: v_dual_min_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_dual_min_f32 v2, v2, v18 :: v_dual_min_f32 v3, v3, v19
+; GFX11-NEXT: v_dual_min_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26
+; GFX11-NEXT: v_dual_min_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_min_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_dual_min_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28
; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_f32_e32 v10, v10, v26
+; GFX11-NEXT: v_min_f32_e32 v26, v52, v51
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_min_f32_e32 v25, v54, v53
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30
-; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_dual_min_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4
-; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_min_f32_e32 v4, v4, v20
-; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_min_f32 v9, v9, v25
-; GFX11-NEXT: v_min_f32_e32 v25, v69, v68
-; GFX11-NEXT: v_dual_min_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3
-; GFX11-NEXT: v_min_f32_e32 v27, v81, v80
-; GFX11-NEXT: v_min_f32_e32 v12, v12, v28
-; GFX11-NEXT: v_dual_min_f32 v28, v83, v82 :: v_dual_min_f32 v29, v85, v84
-; GFX11-NEXT: v_dual_min_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_min_f32_e32 v22, v55, v54
-; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_dual_min_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_min_f32_e32 v24, v64, v55
+; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_min_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_min_f32_e32 v23, v66, v65
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_min_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_dual_min_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_min_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-NEXT: v_dual_min_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_min_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: v_min_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_min_f32_e32 v37, v86, v85
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11-NEXT: v_min_f32_e32 v14, v14, v30
-; GFX11-NEXT: v_dual_min_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_min_f32_e32 v23, v65, v64
-; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT: v_dual_min_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21
-; GFX11-NEXT: v_min_f32_e32 v2, v2, v18
-; GFX11-NEXT: v_dual_min_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16
-; GFX11-NEXT: v_min_f32_e32 v18, v39, v38
-; GFX11-NEXT: v_dual_min_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16
-; GFX11-NEXT: v_min_f32_e32 v19, v49, v48
-; GFX11-NEXT: v_min_f32_e32 v17, v37, v36
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX11-NEXT: v_dual_min_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_min_f32_e32 v21, v53, v52
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302
-; GFX11-NEXT: v_min_f32_e32 v0, v0, v16
-; GFX11-NEXT: v_min_f32_e32 v16, v35, v34
-; GFX11-NEXT: v_min_f32_e32 v32, v33, v32
-; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302
-; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302
-; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302
-; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_min_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31
-; GFX11-NEXT: v_min_f32_e32 v15, v15, v17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_min_f32 v30, v36, v35 :: v_dual_min_f32 v33, v34, v33
+; GFX11-NEXT: v_dual_min_f32 v34, v80, v71 :: v_dual_min_f32 v35, v82, v81
+; GFX11-NEXT: v_min_f32_e32 v36, v84, v83
+; GFX11-NEXT: v_dual_min_f32 v16, v32, v16 :: v_dual_min_f32 v15, v15, v17
+; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <32 x bfloat> @llvm.minnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b)
@@ -15553,83 +15404,52 @@ define <3 x bfloat> @v_maxnum_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b) {
; GFX8-LABEL: v_maxnum_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_max_f32_e32 v4, v5, v4
+; GFX8-NEXT: v_max_f32_e32 v3, v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_max_f32_e32 v2, v4, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maxnum_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_max_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_max_f32_e32 v3, v4, v3
; GFX9-NEXT: v_max_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_max_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maxnum_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_max_f32_e32 v4, v5, v4
; GFX10-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_max_f32_e32 v2, v7, v6
; GFX10-NEXT: v_max_f32_e32 v1, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_maxnum_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_max_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <3 x bfloat> @llvm.maxnum.v3bf16(<3 x bfloat> %a, <3 x bfloat> %b)
ret <3 x bfloat> %op
}
@@ -15696,82 +15516,81 @@ define <4 x bfloat> @v_maxnum_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b) {
; GFX8-LABEL: v_maxnum_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_max_f32_e32 v4, v5, v4
; GFX8-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_max_f32_e32 v2, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_max_f32_e32 v0, v0, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_max_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maxnum_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_max_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_max_f32_e32 v4, v5, v4
+; GFX9-NEXT: v_max_f32_e32 v3, v5, v3
; GFX9-NEXT: v_max_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_max_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maxnum_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_max_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_max_f32_e32 v5, v7, v6
; GFX10-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_max_f32_e32 v2, v7, v6
; GFX10-NEXT: v_max_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maxnum_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX11-NEXT: v_max_f32_e32 v2, v7, v6
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_max_f32 v0, v0, v2 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_dual_max_f32 v4, v5, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_max_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_max_f32_e32 v5, v7, v6
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v5, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.maxnum.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b)
ret <4 x bfloat> %op
@@ -15887,138 +15706,138 @@ define <8 x bfloat> @v_maxnum_v8bf16(<8 x bfloat> %a, <8 x bfloat> %b) {
; GFX8-LABEL: v_maxnum_v8bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v3, v3, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_max_f32_e32 v7, v9, v7
+; GFX8-NEXT: v_max_f32_e32 v2, v2, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_max_f32_e32 v6, v9, v6
; GFX8-NEXT: v_max_f32_e32 v1, v1, v5
-; GFX8-NEXT: v_max_f32_e32 v4, v8, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX8-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v4, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX8-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_max_f32_e32 v3, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_max_f32_e32 v0, v0, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v4, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v5, v9, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v5, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v7, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maxnum_v8bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_max_f32_e32 v3, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_max_f32_e32 v7, v9, v7
+; GFX9-NEXT: v_max_f32_e32 v2, v2, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_max_f32_e32 v6, v9, v6
+; GFX9-NEXT: v_max_f32_e32 v1, v1, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
+; GFX9-NEXT: v_max_f32_e32 v5, v9, v5
; GFX9-NEXT: v_max_f32_e32 v0, v0, v4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_max_f32_e32 v4, v8, v4
-; GFX9-NEXT: v_max_f32_e32 v1, v1, v5
-; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_max_f32_e32 v2, v2, v5
-; GFX9-NEXT: v_perm_b32 v2, v2, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX9-NEXT: v_max_f32_e32 v4, v5, v4
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v7
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_max_f32_e32 v3, v3, v5
-; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v5, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v7, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maxnum_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_max_f32_e32 v8, v9, v8
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_max_f32_e32 v9, v11, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_max_f32_e32 v8, v9, v8
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_max_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_max_f32_e32 v4, v11, v10
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_max_f32_e32 v10, v11, v10
+; GFX10-NEXT: v_max_f32_e32 v11, v13, v12
+; GFX10-NEXT: v_max_f32_e32 v0, v0, v4
; GFX10-NEXT: v_max_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_max_f32_e32 v5, v10, v9
; GFX10-NEXT: v_max_f32_e32 v2, v2, v6
-; GFX10-NEXT: v_max_f32_e32 v6, v12, v11
; GFX10-NEXT: v_max_f32_e32 v3, v3, v7
-; GFX10-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maxnum_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_max_f32 v9, v11, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_max_f32_e32 v0, v0, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v3
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v5 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v4
-; GFX11-NEXT: v_max_f32_e32 v4, v11, v10
-; GFX11-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_lshlrev_b32 v9, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v7
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_max_f32_e32 v5, v10, v9
-; GFX11-NEXT: v_perm_b32 v0, v0, v8, 0x7060302
-; GFX11-NEXT: v_max_f32_e32 v2, v2, v6
-; GFX11-NEXT: v_max_f32_e32 v6, v12, v11
+; GFX11-NEXT: v_dual_max_f32 v1, v1, v5 :: v_dual_and_b32 v6, 0xffff0000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_max_f32 v2, v2, v6 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_max_f32_e32 v3, v3, v7
-; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v2, v2, v5, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v6, 0x7060302
+; GFX11-NEXT: v_dual_max_f32 v10, v11, v10 :: v_dual_max_f32 v11, v13, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v1, v1, v10, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v11, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <8 x bfloat> @llvm.maxnum.v8bf16(<8 x bfloat> %a, <8 x bfloat> %b)
ret <8 x bfloat> %op
@@ -16234,252 +16053,254 @@ define <16 x bfloat> @v_maxnum_v16bf16(<16 x bfloat> %a, <16 x bfloat> %b) {
; GFX8-LABEL: v_maxnum_v16bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_max_f32_e32 v0, v0, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
; GFX8-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v7, v7, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_max_f32_e32 v15, v17, v15
+; GFX8-NEXT: v_max_f32_e32 v6, v6, v14
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_max_f32_e32 v14, v17, v14
+; GFX8-NEXT: v_max_f32_e32 v5, v5, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_max_f32_e32 v13, v17, v13
+; GFX8-NEXT: v_max_f32_e32 v4, v4, v12
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_max_f32_e32 v12, v17, v12
+; GFX8-NEXT: v_max_f32_e32 v3, v3, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_max_f32_e32 v11, v17, v11
+; GFX8-NEXT: v_max_f32_e32 v2, v2, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v1
; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_max_f32_e32 v10, v17, v10
; GFX8-NEXT: v_max_f32_e32 v1, v1, v9
-; GFX8-NEXT: v_max_f32_e32 v8, v16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_max_f32_e32 v2, v2, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_max_f32_e32 v3, v3, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_max_f32_e32 v4, v4, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_max_f32_e32 v5, v5, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_max_f32_e32 v6, v6, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v8, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX8-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_max_f32_e32 v7, v7, v9
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_max_f32_e32 v0, v0, v8
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v8, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v9, v17, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v9, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v10, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v11, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v12, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v13, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v14, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v15, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maxnum_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_max_f32_e32 v7, v7, v15
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_max_f32_e32 v15, v17, v15
+; GFX9-NEXT: v_max_f32_e32 v6, v6, v14
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_max_f32_e32 v14, v17, v14
+; GFX9-NEXT: v_max_f32_e32 v5, v5, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_max_f32_e32 v13, v17, v13
+; GFX9-NEXT: v_max_f32_e32 v4, v4, v12
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_max_f32_e32 v12, v17, v12
+; GFX9-NEXT: v_max_f32_e32 v3, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_max_f32_e32 v11, v17, v11
+; GFX9-NEXT: v_max_f32_e32 v2, v2, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_max_f32_e32 v10, v17, v10
+; GFX9-NEXT: v_max_f32_e32 v1, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v8
; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v0
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
+; GFX9-NEXT: v_max_f32_e32 v9, v17, v9
; GFX9-NEXT: v_max_f32_e32 v0, v0, v8
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_max_f32_e32 v8, v16, v8
-; GFX9-NEXT: v_max_f32_e32 v1, v1, v9
-; GFX9-NEXT: v_perm_b32 v1, v1, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v2
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v10
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_max_f32_e32 v2, v2, v9
-; GFX9-NEXT: v_perm_b32 v2, v2, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v11
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_max_f32_e32 v3, v3, v9
-; GFX9-NEXT: v_perm_b32 v3, v3, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v4
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v12
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_max_f32_e32 v4, v4, v9
-; GFX9-NEXT: v_perm_b32 v4, v4, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v13
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v13
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_max_f32_e32 v5, v5, v9
-; GFX9-NEXT: v_perm_b32 v5, v5, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v6
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v14
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_max_f32_e32 v6, v6, v9
-; GFX9-NEXT: v_perm_b32 v6, v6, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v15
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v7
-; GFX9-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v15
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_max_f32_e32 v7, v7, v9
-; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v9, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v11, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v13, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v14, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v15, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maxnum_v16bf16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v5
; GFX10-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX10-NEXT: v_max_f32_e32 v7, v7, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX10-NEXT: v_max_f32_e32 v15, v17, v15
+; GFX10-NEXT: v_max_f32_e32 v6, v6, v14
+; GFX10-NEXT: v_max_f32_e32 v14, v19, v18
+; GFX10-NEXT: v_max_f32_e32 v5, v5, v13
+; GFX10-NEXT: v_max_f32_e32 v13, v21, v20
+; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v10
; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_max_f32_e32 v17, v18, v17
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_max_f32_e32 v18, v20, v19
; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX10-NEXT: v_max_f32_e32 v19, v20, v19
+; GFX10-NEXT: v_max_f32_e32 v20, v22, v21
; GFX10-NEXT: v_max_f32_e32 v0, v0, v8
-; GFX10-NEXT: v_max_f32_e32 v8, v18, v17
; GFX10-NEXT: v_max_f32_e32 v1, v1, v9
-; GFX10-NEXT: v_max_f32_e32 v9, v20, v19
; GFX10-NEXT: v_max_f32_e32 v2, v2, v10
-; GFX10-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v11
-; GFX10-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX10-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX10-NEXT: v_max_f32_e32 v8, v9, v8
-; GFX10-NEXT: v_max_f32_e32 v3, v3, v10
-; GFX10-NEXT: v_max_f32_e32 v9, v16, v11
+; GFX10-NEXT: v_max_f32_e32 v3, v3, v11
; GFX10-NEXT: v_max_f32_e32 v4, v4, v12
-; GFX10-NEXT: v_max_f32_e32 v10, v18, v17
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX10-NEXT: v_lshlrev_b32_e32 v13, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_max_f32_e32 v5, v5, v11
-; GFX10-NEXT: v_max_f32_e32 v11, v13, v12
-; GFX10-NEXT: v_max_f32_e32 v6, v6, v14
-; GFX10-NEXT: v_max_f32_e32 v12, v17, v16
-; GFX10-NEXT: v_max_f32_e32 v7, v7, v15
-; GFX10-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX10-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maxnum_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_max_f32_e32 v2, v2, v10
-; GFX11-NEXT: v_dual_max_f32 v16, v17, v16 :: v_dual_lshlrev_b32 v17, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v9 :: v_dual_and_b32 v10, 0xffff0000, v11
-; GFX11-NEXT: v_max_f32_e32 v9, v20, v19
-; GFX11-NEXT: v_perm_b32 v2, v2, v9, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v10 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v8
-; GFX11-NEXT: v_max_f32_e32 v8, v18, v17
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v8, 0x7060302
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v13
+; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_dual_max_f32 v10, v18, v17 :: v_dual_lshlrev_b32 v17, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_dual_max_f32 v4, v4, v12 :: v_dual_and_b32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_dual_max_f32 v8, v9, v8 :: v_dual_max_f32 v9, v16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v4, v4, v12 :: v_dual_and_b32 v5, 0xffff0000, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v15
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v7
+; GFX11-NEXT: v_max_f32_e32 v5, v5, v13
+; GFX11-NEXT: v_max_f32_e32 v13, v21, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_dual_max_f32 v16, v17, v16 :: v_dual_and_b32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v0, v0, v8 :: v_dual_and_b32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_perm_b32 v4, v4, v13, 0x7060302
+; GFX11-NEXT: v_max_f32_e32 v7, v7, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_perm_b32 v3, v3, v8, 0x7060302
-; GFX11-NEXT: v_max_f32_e32 v5, v5, v11
-; GFX11-NEXT: v_max_f32_e32 v11, v13, v12
-; GFX11-NEXT: v_max_f32_e32 v12, v17, v16
-; GFX11-NEXT: v_dual_max_f32 v6, v6, v14 :: v_dual_max_f32 v7, v7, v15
-; GFX11-NEXT: v_perm_b32 v4, v4, v9, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v10, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v6, v6, v11, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v12, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v7, v7, v16, 0x7060302
+; GFX11-NEXT: v_max_f32_e32 v15, v17, v15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v6, v6, v14 :: v_dual_lshlrev_b32 v17, 16, v11
+; GFX11-NEXT: v_max_f32_e32 v14, v19, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v10
+; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_max_f32 v17, v18, v17 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_perm_b32 v5, v5, v14, 0x7060302
+; GFX11-NEXT: v_perm_b32 v6, v6, v15, 0x7060302
+; GFX11-NEXT: v_max_f32_e32 v3, v3, v11
+; GFX11-NEXT: v_dual_max_f32 v18, v20, v19 :: v_dual_lshlrev_b32 v19, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_dual_max_f32 v2, v2, v10 :: v_dual_and_b32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_perm_b32 v3, v3, v17, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_max_f32 v19, v20, v19 :: v_dual_max_f32 v20, v22, v21
+; GFX11-NEXT: v_max_f32_e32 v1, v1, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v20, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <16 x bfloat> @llvm.maxnum.v16bf16(<16 x bfloat> %a, <16 x bfloat> %b)
ret <16 x bfloat> %op
@@ -17015,483 +16836,480 @@ define <32 x bfloat> @v_maxnum_v32bf16(<32 x bfloat> %a, <32 x bfloat> %b) {
; GFX8-LABEL: v_maxnum_v32bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX8-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX8-NEXT: v_max_f32_e32 v31, v32, v31
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v31, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX8-NEXT: v_max_f32_e32 v30, v14, v30
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX8-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX8-NEXT: v_max_f32_e32 v14, v32, v14
+; GFX8-NEXT: v_max_f32_e32 v13, v13, v29
+; GFX8-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX8-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX8-NEXT: v_max_f32_e32 v29, v32, v29
+; GFX8-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX8-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX8-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX8-NEXT: v_max_f32_e32 v28, v32, v28
+; GFX8-NEXT: v_max_f32_e32 v11, v11, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX8-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX8-NEXT: v_max_f32_e32 v27, v32, v27
+; GFX8-NEXT: v_max_f32_e32 v10, v10, v26
+; GFX8-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX8-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX8-NEXT: v_max_f32_e32 v26, v32, v26
+; GFX8-NEXT: v_max_f32_e32 v9, v9, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX8-NEXT: v_max_f32_e32 v8, v8, v24
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX8-NEXT: v_max_f32_e32 v25, v32, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX8-NEXT: v_alignbit_b32 v8, v8, v25, 16
+; GFX8-NEXT: v_alignbit_b32 v9, v9, v26, 16
+; GFX8-NEXT: v_alignbit_b32 v10, v10, v27, 16
+; GFX8-NEXT: v_alignbit_b32 v11, v11, v28, 16
+; GFX8-NEXT: v_alignbit_b32 v12, v12, v29, 16
+; GFX8-NEXT: v_alignbit_b32 v13, v13, v14, 16
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX8-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX8-NEXT: v_max_f32_e32 v32, v32, v33
+; GFX8-NEXT: v_max_f32_e32 v15, v15, v24
+; GFX8-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX8-NEXT: v_max_f32_e32 v24, v33, v24
+; GFX8-NEXT: v_max_f32_e32 v7, v7, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX8-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_max_f32_e32 v23, v33, v23
+; GFX8-NEXT: v_max_f32_e32 v6, v6, v22
+; GFX8-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX8-NEXT: v_max_f32_e32 v22, v33, v22
+; GFX8-NEXT: v_max_f32_e32 v5, v5, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_max_f32_e32 v21, v33, v21
+; GFX8-NEXT: v_max_f32_e32 v4, v4, v20
+; GFX8-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_max_f32_e32 v20, v33, v20
+; GFX8-NEXT: v_max_f32_e32 v3, v3, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_max_f32_e32 v19, v33, v19
+; GFX8-NEXT: v_max_f32_e32 v2, v2, v18
+; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_max_f32_e32 v18, v33, v18
; GFX8-NEXT: v_max_f32_e32 v1, v1, v17
-; GFX8-NEXT: v_max_f32_e32 v16, v31, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX8-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX8-NEXT: v_max_f32_e32 v17, v33, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX8-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_max_f32_e32 v2, v2, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v2, v2, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX8-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_max_f32_e32 v3, v3, v17
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v3, v3, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX8-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX8-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_max_f32_e32 v4, v4, v17
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_alignbit_b32 v4, v4, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v5
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v21
-; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX8-NEXT: v_max_f32_e32 v5, v5, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_alignbit_b32 v5, v5, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v6
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v22
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_max_f32_e32 v6, v6, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_alignbit_b32 v6, v6, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v7
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v23
-; GFX8-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX8-NEXT: v_max_f32_e32 v7, v7, v18
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_alignbit_b32 v7, v7, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v8
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v24
-; GFX8-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX8-NEXT: v_max_f32_e32 v8, v8, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_alignbit_b32 v8, v8, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v9
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v25
-; GFX8-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX8-NEXT: v_max_f32_e32 v9, v9, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_alignbit_b32 v9, v9, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v10
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v26
-; GFX8-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX8-NEXT: v_max_f32_e32 v10, v10, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_alignbit_b32 v10, v10, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v11
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v27
-; GFX8-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX8-NEXT: v_max_f32_e32 v11, v11, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_alignbit_b32 v11, v11, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v12
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v28
-; GFX8-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX8-NEXT: v_max_f32_e32 v12, v12, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_alignbit_b32 v12, v12, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v13
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v29
-; GFX8-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX8-NEXT: v_max_f32_e32 v13, v13, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_alignbit_b32 v13, v13, v16, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
-; GFX8-NEXT: v_and_b32_e32 v18, 0xffff0000, v30
-; GFX8-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX8-NEXT: v_max_f32_e32 v14, v14, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_alignbit_b32 v14, v14, v16, 16
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX8-NEXT: v_lshlrev_b32_e32 v18, 16, v15
-; GFX8-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX8-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX8-NEXT: v_max_f32_e32 v15, v15, v17
-; GFX8-NEXT: v_max_f32_e32 v16, v18, v16
; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_alignbit_b32 v15, v15, v16, 16
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v30
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v17, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v18, 16
+; GFX8-NEXT: v_alignbit_b32 v2, v2, v19, 16
+; GFX8-NEXT: v_alignbit_b32 v3, v3, v20, 16
+; GFX8-NEXT: v_alignbit_b32 v4, v4, v21, 16
+; GFX8-NEXT: v_alignbit_b32 v5, v5, v22, 16
+; GFX8-NEXT: v_alignbit_b32 v6, v6, v23, 16
+; GFX8-NEXT: v_alignbit_b32 v7, v7, v24, 16
+; GFX8-NEXT: v_alignbit_b32 v14, v16, v31, 16
+; GFX8-NEXT: v_alignbit_b32 v15, v15, v32, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maxnum_v32bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v16
-; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v14
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX9-NEXT: v_max_f32_e32 v31, v32, v31
-; GFX9-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_max_f32_e32 v14, v14, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v13
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX9-NEXT: v_max_f32_e32 v30, v32, v30
+; GFX9-NEXT: v_max_f32_e32 v13, v13, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v12
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX9-NEXT: v_max_f32_e32 v29, v32, v29
+; GFX9-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v11
+; GFX9-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX9-NEXT: v_max_f32_e32 v28, v32, v28
+; GFX9-NEXT: v_max_f32_e32 v11, v11, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v10
+; GFX9-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX9-NEXT: v_max_f32_e32 v27, v32, v27
+; GFX9-NEXT: v_max_f32_e32 v10, v10, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v9
+; GFX9-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX9-NEXT: v_max_f32_e32 v26, v32, v26
+; GFX9-NEXT: v_max_f32_e32 v9, v9, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v8
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX9-NEXT: v_max_f32_e32 v8, v8, v24
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32
+; GFX9-NEXT: v_max_f32_e32 v25, v32, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v1
+; GFX9-NEXT: v_perm_b32 v8, v8, v25, s4
+; GFX9-NEXT: v_perm_b32 v9, v9, v26, s4
+; GFX9-NEXT: v_perm_b32 v10, v10, v27, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v28, s4
+; GFX9-NEXT: v_perm_b32 v12, v12, v29, s4
+; GFX9-NEXT: v_perm_b32 v13, v13, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v24
+; GFX9-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX9-NEXT: v_max_f32_e32 v32, v32, v33
+; GFX9-NEXT: v_max_f32_e32 v15, v15, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v7
+; GFX9-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_max_f32_e32 v24, v33, v24
+; GFX9-NEXT: v_max_f32_e32 v7, v7, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v6
+; GFX9-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_max_f32_e32 v23, v33, v23
+; GFX9-NEXT: v_max_f32_e32 v6, v6, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v5
+; GFX9-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_max_f32_e32 v22, v33, v22
+; GFX9-NEXT: v_max_f32_e32 v5, v5, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_max_f32_e32 v21, v33, v21
+; GFX9-NEXT: v_max_f32_e32 v4, v4, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_max_f32_e32 v20, v33, v20
+; GFX9-NEXT: v_max_f32_e32 v3, v3, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v2
+; GFX9-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_max_f32_e32 v19, v33, v19
+; GFX9-NEXT: v_max_f32_e32 v2, v2, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v1
; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_max_f32_e32 v16, v31, v16
+; GFX9-NEXT: v_max_f32_e32 v18, v33, v18
; GFX9-NEXT: v_max_f32_e32 v1, v1, v17
-; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_max_f32_e32 v2, v2, v17
-; GFX9-NEXT: v_perm_b32 v2, v2, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v19
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_max_f32_e32 v3, v3, v17
-; GFX9-NEXT: v_perm_b32 v3, v3, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v20
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v4
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v20
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX9-NEXT: v_max_f32_e32 v4, v4, v17
-; GFX9-NEXT: v_perm_b32 v4, v4, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v21
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v21
-; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX9-NEXT: v_max_f32_e32 v5, v5, v17
-; GFX9-NEXT: v_perm_b32 v5, v5, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v22
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v6
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v22
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_max_f32_e32 v6, v6, v17
-; GFX9-NEXT: v_perm_b32 v6, v6, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v23
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v7
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v23
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX9-NEXT: v_max_f32_e32 v7, v7, v17
-; GFX9-NEXT: v_perm_b32 v7, v7, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v8
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v24
-; GFX9-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX9-NEXT: v_max_f32_e32 v8, v8, v17
-; GFX9-NEXT: v_perm_b32 v8, v8, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v25
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v25
-; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX9-NEXT: v_max_f32_e32 v9, v9, v17
-; GFX9-NEXT: v_perm_b32 v9, v9, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v26
-; GFX9-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX9-NEXT: v_max_f32_e32 v10, v10, v17
-; GFX9-NEXT: v_perm_b32 v10, v10, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v27
-; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX9-NEXT: v_max_f32_e32 v11, v11, v17
-; GFX9-NEXT: v_perm_b32 v11, v11, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v12
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v28
-; GFX9-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX9-NEXT: v_max_f32_e32 v12, v12, v17
-; GFX9-NEXT: v_perm_b32 v12, v12, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v29
-; GFX9-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX9-NEXT: v_max_f32_e32 v13, v13, v17
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v30
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v14
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v30
-; GFX9-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX9-NEXT: v_max_f32_e32 v14, v14, v17
-; GFX9-NEXT: v_perm_b32 v14, v14, v16, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX9-NEXT: v_max_f32_e32 v16, v17, v16
-; GFX9-NEXT: v_and_b32_e32 v17, 0xffff0000, v18
-; GFX9-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX9-NEXT: v_max_f32_e32 v15, v15, v17
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v33, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_max_f32_e32 v17, v33, v17
+; GFX9-NEXT: v_max_f32_e32 v0, v0, v16
+; GFX9-NEXT: v_perm_b32 v0, v0, v17, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v19, s4
+; GFX9-NEXT: v_perm_b32 v3, v3, v20, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v21, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v22, s4
+; GFX9-NEXT: v_perm_b32 v6, v6, v23, s4
+; GFX9-NEXT: v_perm_b32 v7, v7, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v32, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maxnum_v32bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
+; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
+; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
+; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v14
+; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
+; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
+; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v13
+; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
+; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
+; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_max_f32_e32 v39, v48, v39
+; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v17
+; GFX10-NEXT: v_max_f32_e32 v11, v11, v27
+; GFX10-NEXT: v_lshlrev_b32_e32 v27, 16, v1
; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX10-NEXT: v_max_f32_e32 v5, v5, v21
-; GFX10-NEXT: v_max_f32_e32 v21, v53, v52
-; GFX10-NEXT: v_max_f32_e32 v6, v6, v22
-; GFX10-NEXT: v_max_f32_e32 v22, v55, v54
-; GFX10-NEXT: v_max_f32_e32 v7, v7, v23
-; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v25
-; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v9
+; GFX10-NEXT: v_max_f32_e32 v49, v50, v49
+; GFX10-NEXT: v_lshlrev_b32_e32 v50, 16, v16
+; GFX10-NEXT: v_max_f32_e32 v10, v10, v26
+; GFX10-NEXT: v_lshlrev_b32_e32 v26, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX10-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX10-NEXT: v_lshlrev_b32_e32 v52, 16, v9
; GFX10-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX10-NEXT: v_max_f32_e32 v32, v33, v32
-; GFX10-NEXT: v_lshlrev_b32_e32 v33, 16, v10
-; GFX10-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX10-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
+; GFX10-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX10-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX10-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
+; GFX10-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX10-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX10-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX10-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX10-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX10-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX10-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_max_f32_e32 v33, v34, v33
+; GFX10-NEXT: v_lshlrev_b32_e32 v34, 16, v20
+; GFX10-NEXT: v_max_f32_e32 v14, v14, v30
+; GFX10-NEXT: v_lshlrev_b32_e32 v30, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX10-NEXT: v_max_f32_e32 v35, v36, v35
+; GFX10-NEXT: v_lshlrev_b32_e32 v36, 16, v19
+; GFX10-NEXT: v_max_f32_e32 v13, v13, v29
+; GFX10-NEXT: v_lshlrev_b32_e32 v29, 16, v3
+; GFX10-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_max_f32_e32 v37, v38, v37
+; GFX10-NEXT: v_lshlrev_b32_e32 v38, 16, v18
+; GFX10-NEXT: v_max_f32_e32 v12, v12, v28
+; GFX10-NEXT: v_lshlrev_b32_e32 v28, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v27
-; GFX10-NEXT: v_max_f32_e32 v34, v35, v34
-; GFX10-NEXT: v_lshlrev_b32_e32 v35, 16, v11
-; GFX10-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX10-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
; GFX10-NEXT: v_max_f32_e32 v1, v1, v17
-; GFX10-NEXT: v_lshlrev_b32_e32 v17, 16, v28
-; GFX10-NEXT: v_max_f32_e32 v36, v37, v36
-; GFX10-NEXT: v_lshlrev_b32_e32 v37, 16, v12
-; GFX10-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX10-NEXT: v_max_f32_e32 v51, v52, v51
+; GFX10-NEXT: v_max_f32_e32 v9, v9, v25
+; GFX10-NEXT: v_max_f32_e32 v25, v54, v53
+; GFX10-NEXT: v_max_f32_e32 v8, v8, v24
+; GFX10-NEXT: v_max_f32_e32 v24, v64, v55
+; GFX10-NEXT: v_max_f32_e32 v7, v7, v23
+; GFX10-NEXT: v_max_f32_e32 v23, v66, v65
+; GFX10-NEXT: v_max_f32_e32 v6, v6, v22
+; GFX10-NEXT: v_max_f32_e32 v22, v68, v67
+; GFX10-NEXT: v_max_f32_e32 v5, v5, v21
+; GFX10-NEXT: v_max_f32_e32 v21, v30, v34
+; GFX10-NEXT: v_max_f32_e32 v29, v29, v36
+; GFX10-NEXT: v_max_f32_e32 v28, v28, v38
+; GFX10-NEXT: v_max_f32_e32 v27, v27, v48
+; GFX10-NEXT: v_max_f32_e32 v26, v26, v50
; GFX10-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX10-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; GFX10-NEXT: v_max_f32_e32 v38, v39, v38
-; GFX10-NEXT: v_lshlrev_b32_e32 v39, 16, v13
-; GFX10-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
-; GFX10-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
; GFX10-NEXT: v_max_f32_e32 v3, v3, v19
-; GFX10-NEXT: v_lshlrev_b32_e32 v19, 16, v30
-; GFX10-NEXT: v_max_f32_e32 v48, v49, v48
-; GFX10-NEXT: v_lshlrev_b32_e32 v49, 16, v14
-; GFX10-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX10-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
; GFX10-NEXT: v_max_f32_e32 v4, v4, v20
-; GFX10-NEXT: v_lshlrev_b32_e32 v20, 16, v15
-; GFX10-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX10-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX10-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX10-NEXT: v_max_f32_e32 v50, v51, v50
-; GFX10-NEXT: v_max_f32_e32 v23, v65, v64
-; GFX10-NEXT: v_max_f32_e32 v8, v8, v24
-; GFX10-NEXT: v_max_f32_e32 v24, v67, v66
-; GFX10-NEXT: v_max_f32_e32 v9, v9, v25
-; GFX10-NEXT: v_max_f32_e32 v25, v33, v68
-; GFX10-NEXT: v_max_f32_e32 v10, v10, v26
-; GFX10-NEXT: v_max_f32_e32 v16, v35, v16
-; GFX10-NEXT: v_max_f32_e32 v11, v11, v27
-; GFX10-NEXT: v_max_f32_e32 v17, v37, v17
-; GFX10-NEXT: v_max_f32_e32 v12, v12, v28
-; GFX10-NEXT: v_max_f32_e32 v18, v39, v18
-; GFX10-NEXT: v_max_f32_e32 v13, v13, v29
-; GFX10-NEXT: v_max_f32_e32 v19, v49, v19
-; GFX10-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX10-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v34, 0x7060302
-; GFX10-NEXT: v_perm_b32 v2, v2, v36, 0x7060302
-; GFX10-NEXT: v_perm_b32 v3, v3, v38, 0x7060302
-; GFX10-NEXT: v_perm_b32 v4, v4, v48, 0x7060302
-; GFX10-NEXT: v_perm_b32 v5, v5, v50, 0x7060302
-; GFX10-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX10-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX10-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX10-NEXT: v_perm_b32 v11, v11, v16, 0x7060302
-; GFX10-NEXT: v_perm_b32 v12, v12, v17, 0x7060302
-; GFX10-NEXT: v_perm_b32 v13, v13, v18, 0x7060302
-; GFX10-NEXT: v_perm_b32 v14, v14, v19, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v27, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v26, 0x7060302
+; GFX10-NEXT: v_perm_b32 v2, v2, v28, 0x7060302
+; GFX10-NEXT: v_perm_b32 v3, v3, v29, 0x7060302
+; GFX10-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX10-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX10-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
+; GFX10-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX10-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX10-NEXT: v_perm_b32 v9, v9, v51, 0x7060302
+; GFX10-NEXT: v_perm_b32 v10, v10, v49, 0x7060302
+; GFX10-NEXT: v_perm_b32 v11, v11, v39, 0x7060302
+; GFX10-NEXT: v_perm_b32 v12, v12, v37, 0x7060302
+; GFX10-NEXT: v_perm_b32 v13, v13, v35, 0x7060302
+; GFX10-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v21, 16, v31
-; GFX10-NEXT: v_and_b32_e32 v22, 0xffff0000, v31
-; GFX10-NEXT: v_max_f32_e32 v20, v20, v21
-; GFX10-NEXT: v_max_f32_e32 v15, v15, v22
-; GFX10-NEXT: v_perm_b32 v15, v15, v20, 0x7060302
+; GFX10-NEXT: v_lshlrev_b32_e32 v16, 16, v31
+; GFX10-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX10-NEXT: v_max_f32_e32 v16, v32, v16
+; GFX10-NEXT: v_max_f32_e32 v15, v15, v17
+; GFX10-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maxnum_v32bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v10
-; GFX11-NEXT: v_and_b32_e32 v26, 0xffff0000, v26
-; GFX11-NEXT: v_and_b32_e32 v10, 0xffff0000, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v24
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v8
-; GFX11-NEXT: v_and_b32_e32 v24, 0xffff0000, v24
-; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v5
-; GFX11-NEXT: v_dual_max_f32 v10, v10, v26 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v17
+; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v0
+; GFX11-NEXT: v_and_b32_e32 v16, 0xffff0000, v16
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v11
+; GFX11-NEXT: v_dual_max_f32 v0, v0, v16 :: v_dual_and_b32 v11, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v21
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v51, 16, v25
+; GFX11-NEXT: v_and_b32_e32 v21, 0xffff0000, v21
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_and_b32_e32 v20, 0xffff0000, v20
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v55, 16, v23
+; GFX11-NEXT: v_lshlrev_b32_e32 v71, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v3
; GFX11-NEXT: v_and_b32_e32 v25, 0xffff0000, v25
-; GFX11-NEXT: v_and_b32_e32 v27, 0xffff0000, v27
-; GFX11-NEXT: v_and_b32_e32 v11, 0xffff0000, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v80, 16, v28
-; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v22
+; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v81, 16, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v24
+; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_and_b32 v24, 0xffff0000, v24
+; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_lshlrev_b32 v50, 16, v10
+; GFX11-NEXT: v_dual_max_f32 v21, v70, v69 :: v_dual_and_b32 v10, 0xffff0000, v10
+; GFX11-NEXT: v_dual_max_f32 v2, v2, v18 :: v_dual_max_f32 v3, v3, v19
+; GFX11-NEXT: v_dual_max_f32 v4, v4, v20 :: v_dual_lshlrev_b32 v49, 16, v26
+; GFX11-NEXT: v_dual_max_f32 v9, v9, v25 :: v_dual_and_b32 v26, 0xffff0000, v26
+; GFX11-NEXT: v_max_f32_e32 v6, v6, v22
+; GFX11-NEXT: v_dual_max_f32 v22, v68, v67 :: v_dual_lshlrev_b32 v37, 16, v28
; GFX11-NEXT: v_and_b32_e32 v28, 0xffff0000, v28
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v82, 16, v29
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_max_f32_e32 v10, v10, v26
+; GFX11-NEXT: v_max_f32_e32 v26, v52, v51
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0x7060302
+; GFX11-NEXT: v_max_f32_e32 v25, v54, v53
+; GFX11-NEXT: v_perm_b32 v5, v5, v22, 0x7060302
+; GFX11-NEXT: v_perm_b32 v9, v9, v26, 0x7060302
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_and_b32_e32 v23, 0xffff0000, v23
-; GFX11-NEXT: v_and_b32_e32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v31
+; GFX11-NEXT: v_and_b32_e32 v8, 0xffff0000, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v13
; GFX11-NEXT: v_and_b32_e32 v13, 0xffff0000, v13
-; GFX11-NEXT: v_lshlrev_b32_e32 v84, 16, v30
-; GFX11-NEXT: v_lshlrev_b32_e32 v85, 16, v14
-; GFX11-NEXT: v_and_b32_e32 v22, 0xffff0000, v22
-; GFX11-NEXT: v_and_b32_e32 v30, 0xffff0000, v30
-; GFX11-NEXT: v_and_b32_e32 v14, 0xffff0000, v14
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v86, 16, v15
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v9
-; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v20, 0xffff0000, v20
-; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
-; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX11-NEXT: v_dual_max_f32 v26, v71, v70 :: v_dual_lshlrev_b32 v49, 16, v4
-; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_and_b32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v37, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_max_f32_e32 v4, v4, v20
-; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_max_f32 v9, v9, v25
-; GFX11-NEXT: v_max_f32_e32 v25, v69, v68
-; GFX11-NEXT: v_dual_max_f32 v20, v51, v50 :: v_dual_lshlrev_b32 v39, 16, v3
-; GFX11-NEXT: v_max_f32_e32 v27, v81, v80
-; GFX11-NEXT: v_max_f32_e32 v12, v12, v28
-; GFX11-NEXT: v_dual_max_f32 v28, v83, v82 :: v_dual_max_f32 v29, v85, v84
-; GFX11-NEXT: v_dual_max_f32 v6, v6, v22 :: v_dual_and_b32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_max_f32_e32 v22, v55, v54
-; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_and_b32_e32 v17, 0xffff0000, v17
-; GFX11-NEXT: v_and_b32_e32 v18, 0xffff0000, v18
+; GFX11-NEXT: v_dual_max_f32 v8, v8, v24 :: v_dual_and_b32 v27, 0xffff0000, v27
+; GFX11-NEXT: v_max_f32_e32 v24, v64, v55
+; GFX11-NEXT: v_lshlrev_b32_e32 v38, 16, v12
+; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v29
+; GFX11-NEXT: v_max_f32_e32 v7, v7, v23
+; GFX11-NEXT: v_max_f32_e32 v23, v66, v65
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_max_f32 v12, v12, v28 :: v_dual_and_b32 v29, 0xffff0000, v29
+; GFX11-NEXT: v_dual_max_f32 v28, v48, v39 :: v_dual_lshlrev_b32 v33, 16, v30
+; GFX11-NEXT: v_dual_max_f32 v13, v13, v29 :: v_dual_lshlrev_b32 v34, 16, v14
+; GFX11-NEXT: v_lshlrev_b32_e32 v32, 16, v15
+; GFX11-NEXT: v_dual_max_f32 v11, v11, v27 :: v_dual_and_b32 v14, 0xffff0000, v14
+; GFX11-NEXT: v_dual_max_f32 v27, v50, v49 :: v_dual_and_b32 v30, 0xffff0000, v30
+; GFX11-NEXT: v_max_f32_e32 v29, v38, v37
+; GFX11-NEXT: v_and_b32_e32 v15, 0xffff0000, v15
+; GFX11-NEXT: v_max_f32_e32 v37, v86, v85
+; GFX11-NEXT: v_perm_b32 v6, v6, v23, 0x7060302
; GFX11-NEXT: v_max_f32_e32 v14, v14, v30
-; GFX11-NEXT: v_dual_max_f32 v7, v7, v23 :: v_dual_and_b32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_max_f32_e32 v23, v65, v64
-; GFX11-NEXT: v_and_b32_e32 v19, 0xffff0000, v19
-; GFX11-NEXT: v_dual_max_f32 v24, v67, v66 :: v_dual_and_b32 v21, 0xffff0000, v21
-; GFX11-NEXT: v_max_f32_e32 v2, v2, v18
-; GFX11-NEXT: v_dual_max_f32 v1, v1, v17 :: v_dual_lshlrev_b32 v32, 16, v16
-; GFX11-NEXT: v_max_f32_e32 v18, v39, v38
-; GFX11-NEXT: v_dual_max_f32 v3, v3, v19 :: v_dual_and_b32 v16, 0xffff0000, v16
-; GFX11-NEXT: v_max_f32_e32 v19, v49, v48
-; GFX11-NEXT: v_max_f32_e32 v17, v37, v36
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v0
-; GFX11-NEXT: v_dual_max_f32 v5, v5, v21 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_max_f32_e32 v21, v53, v52
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0x7060302
-; GFX11-NEXT: v_perm_b32 v3, v3, v18, 0x7060302
-; GFX11-NEXT: v_max_f32_e32 v0, v0, v16
-; GFX11-NEXT: v_max_f32_e32 v16, v35, v34
-; GFX11-NEXT: v_max_f32_e32 v32, v33, v32
-; GFX11-NEXT: v_perm_b32 v4, v4, v19, 0x7060302
-; GFX11-NEXT: v_perm_b32 v5, v5, v20, 0x7060302
-; GFX11-NEXT: v_perm_b32 v6, v6, v21, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v16, 0x7060302
-; GFX11-NEXT: v_perm_b32 v0, v0, v32, 0x7060302
-; GFX11-NEXT: v_perm_b32 v7, v7, v22, 0x7060302
-; GFX11-NEXT: v_perm_b32 v8, v8, v23, 0x7060302
-; GFX11-NEXT: v_perm_b32 v9, v9, v24, 0x7060302
-; GFX11-NEXT: v_perm_b32 v10, v10, v25, 0x7060302
-; GFX11-NEXT: v_perm_b32 v11, v11, v26, 0x7060302
-; GFX11-NEXT: v_perm_b32 v12, v12, v27, 0x7060302
-; GFX11-NEXT: v_perm_b32 v13, v13, v28, 0x7060302
-; GFX11-NEXT: v_perm_b32 v14, v14, v29, 0x7060302
-; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_max_f32 v16, v86, v16 :: v_dual_and_b32 v17, 0xffff0000, v31
-; GFX11-NEXT: v_max_f32_e32 v15, v15, v17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_dual_max_f32 v30, v36, v35 :: v_dual_max_f32 v33, v34, v33
+; GFX11-NEXT: v_dual_max_f32 v34, v80, v71 :: v_dual_max_f32 v35, v82, v81
+; GFX11-NEXT: v_max_f32_e32 v36, v84, v83
+; GFX11-NEXT: v_dual_max_f32 v16, v32, v16 :: v_dual_max_f32 v15, v15, v17
+; GFX11-NEXT: v_perm_b32 v0, v0, v37, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v2, v2, v35, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v36, 0x7060302
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0x7060302
+; GFX11-NEXT: v_perm_b32 v7, v7, v24, 0x7060302
+; GFX11-NEXT: v_perm_b32 v8, v8, v25, 0x7060302
+; GFX11-NEXT: v_perm_b32 v10, v10, v27, 0x7060302
+; GFX11-NEXT: v_perm_b32 v11, v11, v28, 0x7060302
+; GFX11-NEXT: v_perm_b32 v12, v12, v29, 0x7060302
+; GFX11-NEXT: v_perm_b32 v13, v13, v30, 0x7060302
+; GFX11-NEXT: v_perm_b32 v14, v14, v33, 0x7060302
; GFX11-NEXT: v_perm_b32 v15, v15, v16, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <32 x bfloat> @llvm.maxnum.v32bf16(<32 x bfloat> %a, <32 x bfloat> %b)
@@ -21043,13 +20861,13 @@ define <3 x i16> @v_fptosi_v3bf16_to_v3i16(<3 x bfloat> %x) {
; GFX8-LABEL: v_fptosi_v3bf16_to_v3i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_cvt_i32_f32_sdwa v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX8-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX8-NEXT: v_cvt_i32_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fptosi_v3bf16_to_v3i16:
@@ -21140,65 +20958,65 @@ define <4 x i16> @v_fptosi_v4bf16_to_v4i16(<4 x bfloat> %x) {
; GFX8-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_cvt_i32_f32_sdwa v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX8-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX8-NEXT: v_cvt_i32_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-; GFX8-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_cvt_i32_f32_e32 v2, v2
+; GFX8-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX8-NEXT: v_cvt_i32_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_cvt_i32_f32_sdwa v1, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX9-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX10-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX10-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX10-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
+; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fptosi_v4bf16_to_v4i16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_i32_f32_e32 v2, v2
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_i32_f32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_i32_f32_e32 v0, v0
; GFX11-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x5040100
+; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = fptosi <4 x bfloat> %x to <4 x i16>
ret <4 x i16> %op
@@ -22538,13 +22356,11 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX8-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v3i16_to_v3bf16:
@@ -22552,11 +22368,10 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX9-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v3, v1, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_sitofp_v3i16_to_v3bf16:
@@ -22564,29 +22379,10 @@ define <3 x bfloat> @v_sitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX10-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_sitofp_v3i16_to_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 16, v0
-; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 16, v1
-; GFX11-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <3 x i16> %x to <3 x bfloat>
ret <3 x bfloat> %op
}
@@ -22629,55 +22425,55 @@ define <4 x bfloat> @v_sitofp_v4i16_to_v4bf16(<4 x i16> %x) {
; GFX8-LABEL: v_sitofp_v4i16_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_i32_sdwa v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_i32_sdwa v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX8-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v4i16_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_i32_sdwa v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX9-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v2, v0, s4
-; GFX9-NEXT: v_perm_b32 v1, v3, v1, s4
+; GFX9-NEXT: v_perm_b32 v0, v3, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_sitofp_v4i16_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f32_i32_sdwa v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_i32_sdwa v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX10-NEXT: v_cvt_f32_i32_sdwa v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX10-NEXT: v_cvt_f32_i32_sdwa v1, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v3, v0, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v2, v1, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_sitofp_v4i16_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_ashrrev_i32_e32 v2, 16, v0
+; GFX11-NEXT: v_ashrrev_i32_e32 v2, 16, v1
+; GFX11-NEXT: v_ashrrev_i32_e32 v3, 16, v0
; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-NEXT: v_ashrrev_i32_e32 v3, 16, v1
; GFX11-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v3, v0, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v2, v1, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <4 x i16> %x to <4 x bfloat>
ret <4 x bfloat> %op
@@ -22813,12 +22609,12 @@ define <3 x bfloat> @v_sitofp_v3i32_to_v3bf16(<3 x i32> %x) {
; GFX8-LABEL: v_sitofp_v3i32_to_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX8-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX8-NEXT: v_cvt_f32_i32_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v3i32_to_v3bf16:
@@ -22875,22 +22671,22 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX8-LABEL: v_sitofp_v4i32_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v4i32_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
@@ -22900,9 +22696,9 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX10-LABEL: v_sitofp_v4i32_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX10-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_i32_e32 v3, v3
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
@@ -22911,11 +22707,11 @@ define <4 x bfloat> @v_sitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX11-LABEL: v_sitofp_v4i32_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
; GFX11-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -23330,130 +23126,130 @@ define <3 x bfloat> @v_sitofp_v3i64_to_v3bf16(<3 x i64> %x) {
; GFX8-LABEL: v_sitofp_v3i64_to_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v7, v0, v1
-; GFX8-NEXT: v_ffbh_i32_e32 v6, v1
+; GFX8-NEXT: v_xor_b32_e32 v7, v4, v5
+; GFX8-NEXT: v_ffbh_i32_e32 v6, v5
; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v7
; GFX8-NEXT: v_add_u32_e32 v6, vcc, -1, v6
; GFX8-NEXT: v_add_u32_e32 v7, vcc, 32, v7
; GFX8-NEXT: v_min_u32_e32 v6, v6, v7
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_xor_b32_e32 v1, v2, v3
-; GFX8-NEXT: v_cvt_f32_i32_e32 v7, v0
-; GFX8-NEXT: v_ffbh_i32_e32 v0, v3
-; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, -1, v0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, 32, v1
-; GFX8-NEXT: v_min_u32_e32 v8, v0, v1
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v6
+; GFX8-NEXT: v_ldexp_f32 v6, v4, v5
+; GFX8-NEXT: v_xor_b32_e32 v5, v0, v1
+; GFX8-NEXT: v_ffbh_i32_e32 v4, v1
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, -1, v4
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 32, v5
+; GFX8-NEXT: v_min_u32_e32 v7, v4, v5
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v7, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX8-NEXT: v_min_u32_e32 v0, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX8-NEXT: v_xor_b32_e32 v5, v2, v3
+; GFX8-NEXT: v_ffbh_i32_e32 v4, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, -1, v4
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 32, v5
+; GFX8-NEXT: v_min_u32_e32 v4, v4, v5
+; GFX8-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 32, v8
-; GFX8-NEXT: v_ldexp_f32 v2, v7, v2
-; GFX8-NEXT: v_ldexp_f32 v3, v0, v1
-; GFX8-NEXT: v_xor_b32_e32 v1, v4, v5
-; GFX8-NEXT: v_ffbh_i32_e32 v0, v5
-; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v1
-; GFX8-NEXT: v_add_u32_e32 v0, vcc, -1, v0
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, 32, v1
-; GFX8-NEXT: v_min_u32_e32 v6, v0, v1
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[4:5]
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v3, v2, 16
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 32, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v7
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v3i64_to_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_xor_b32_e32 v7, v4, v5
+; GFX9-NEXT: v_ffbh_i32_e32 v6, v5
+; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX9-NEXT: v_add_u32_e32 v6, -1, v6
+; GFX9-NEXT: v_add_u32_e32 v7, 32, v7
+; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
; GFX9-NEXT: v_xor_b32_e32 v7, v0, v1
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, 32, v6
; GFX9-NEXT: v_ffbh_i32_e32 v6, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v7
; GFX9-NEXT: v_add_u32_e32 v6, -1, v6
; GFX9-NEXT: v_add_u32_e32 v7, 32, v7
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, v4
; GFX9-NEXT: v_min_u32_e32 v6, v6, v7
; GFX9-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX9-NEXT: v_sub_u32_e32 v6, 32, v6
+; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v0
; GFX9-NEXT: v_xor_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_cvt_f32_i32_e32 v7, v0
; GFX9-NEXT: v_ffbh_i32_e32 v0, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; GFX9-NEXT: v_add_u32_e32 v0, -1, v0
; GFX9-NEXT: v_add_u32_e32 v1, 32, v1
-; GFX9-NEXT: v_min_u32_e32 v8, v0, v1
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
-; GFX9-NEXT: v_ldexp_f32 v2, v7, v6
-; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_xor_b32_e32 v1, v4, v5
-; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v0
-; GFX9-NEXT: v_ffbh_i32_e32 v0, v5
-; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
-; GFX9-NEXT: v_add_u32_e32 v0, -1, v0
-; GFX9-NEXT: v_add_u32_e32 v1, 32, v1
; GFX9-NEXT: v_min_u32_e32 v7, v0, v1
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
-; GFX9-NEXT: v_sub_u32_e32 v6, 32, v8
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[2:3]
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v5
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0
-; GFX9-NEXT: v_ldexp_f32 v3, v3, v6
-; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v3, v2, s4
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, 32, v6
+; GFX9-NEXT: v_ldexp_f32 v1, v2, v1
; GFX9-NEXT: v_sub_u32_e32 v2, 32, v7
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v4, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_sitofp_v3i64_to_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_xor_b32_e32 v7, v0, v1
-; GFX10-NEXT: v_xor_b32_e32 v8, v2, v3
-; GFX10-NEXT: v_xor_b32_e32 v9, v4, v5
-; GFX10-NEXT: v_ffbh_i32_e32 v6, v1
-; GFX10-NEXT: v_ffbh_i32_e32 v10, v3
+; GFX10-NEXT: v_xor_b32_e32 v8, v4, v5
+; GFX10-NEXT: v_xor_b32_e32 v9, v2, v3
+; GFX10-NEXT: v_ffbh_i32_e32 v6, v5
+; GFX10-NEXT: v_ffbh_i32_e32 v10, v1
; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v7
-; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v8
-; GFX10-NEXT: v_ffbh_i32_e32 v11, v5
+; GFX10-NEXT: v_ffbh_i32_e32 v11, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v9, 31, v9
+; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v8
; GFX10-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX10-NEXT: v_add_nc_u32_e32 v7, 32, v7
; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v10
-; GFX10-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX10-NEXT: v_add_nc_u32_e32 v7, 32, v7
; GFX10-NEXT: v_add_nc_u32_e32 v11, -1, v11
; GFX10-NEXT: v_add_nc_u32_e32 v9, 32, v9
-; GFX10-NEXT: v_min_u32_e32 v6, v6, v7
-; GFX10-NEXT: v_min_u32_e32 v7, v10, v8
-; GFX10-NEXT: v_min_u32_e32 v8, v11, v9
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
+; GFX10-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX10-NEXT: v_min_u32_e32 v7, v10, v7
+; GFX10-NEXT: v_min_u32_e32 v9, v11, v9
+; GFX10-NEXT: v_min_u32_e32 v6, v6, v8
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX10-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v6
-; GFX10-NEXT: v_lshlrev_b64 v[2:3], v7, v[2:3]
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
; GFX10-NEXT: v_min_u32_e32 v0, 1, v0
; GFX10-NEXT: v_min_u32_e32 v2, 1, v2
; GFX10-NEXT: v_min_u32_e32 v4, 1, v4
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v7
; GFX10-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 32, v8
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v7
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 32, v9
; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_i32_e32 v1, v1
; GFX10-NEXT: v_cvt_f32_i32_e32 v2, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v6
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v4
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: v_alignbit_b32 v1, s4, v2, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -23579,236 +23375,231 @@ define <4 x bfloat> @v_sitofp_v4i64_to_v4bf16(<4 x i64> %x) {
; GFX8-LABEL: v_sitofp_v4i64_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_xor_b32_e32 v9, v0, v1
-; GFX8-NEXT: v_ffbh_i32_e32 v8, v1
+; GFX8-NEXT: v_xor_b32_e32 v9, v4, v5
+; GFX8-NEXT: v_ffbh_i32_e32 v8, v5
; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v9
; GFX8-NEXT: v_add_u32_e32 v8, vcc, -1, v8
; GFX8-NEXT: v_add_u32_e32 v9, vcc, 32, v9
; GFX8-NEXT: v_min_u32_e32 v8, v8, v9
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_xor_b32_e32 v5, v6, v7
+; GFX8-NEXT: v_cvt_f32_i32_e32 v9, v4
+; GFX8-NEXT: v_ffbh_i32_e32 v4, v7
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX8-NEXT: v_add_u32_e32 v4, vcc, -1, v4
+; GFX8-NEXT: v_add_u32_e32 v5, vcc, 32, v5
+; GFX8-NEXT: v_min_u32_e32 v10, v4, v5
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v10, v[6:7]
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 32, v8
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX8-NEXT: v_ldexp_f32 v5, v9, v6
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 32, v10
+; GFX8-NEXT: v_xor_b32_e32 v7, v0, v1
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX8-NEXT: v_ffbh_i32_e32 v6, v1
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v7
+; GFX8-NEXT: v_add_u32_e32 v6, vcc, -1, v6
+; GFX8-NEXT: v_add_u32_e32 v7, vcc, 32, v7
+; GFX8-NEXT: v_min_u32_e32 v6, v6, v7
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_xor_b32_e32 v1, v2, v3
-; GFX8-NEXT: v_cvt_f32_i32_e32 v9, v0
+; GFX8-NEXT: v_cvt_f32_i32_e32 v7, v0
; GFX8-NEXT: v_ffbh_i32_e32 v0, v3
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; GFX8-NEXT: v_add_u32_e32 v0, vcc, -1, v0
; GFX8-NEXT: v_add_u32_e32 v1, vcc, 32, v1
-; GFX8-NEXT: v_min_u32_e32 v10, v0, v1
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v10, v[2:3]
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v8
+; GFX8-NEXT: v_min_u32_e32 v8, v0, v1
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX8-NEXT: v_ldexp_f32 v3, v9, v2
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 32, v10
-; GFX8-NEXT: v_xor_b32_e32 v2, v4, v5
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_ffbh_i32_e32 v1, v5
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v2
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 32, v2
-; GFX8-NEXT: v_min_u32_e32 v8, v1, v2
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v8, v[4:5]
+; GFX8-NEXT: v_ldexp_f32 v1, v7, v2
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v8
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_xor_b32_e32 v2, v6, v7
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; GFX8-NEXT: v_cvt_f32_i32_e32 v3, v1
-; GFX8-NEXT: v_ffbh_i32_e32 v1, v7
-; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v2
-; GFX8-NEXT: v_add_u32_e32 v1, vcc, -1, v1
-; GFX8-NEXT: v_add_u32_e32 v2, vcc, 32, v2
-; GFX8-NEXT: v_min_u32_e32 v4, v1, v2
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v4, v[6:7]
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v8
-; GFX8-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX8-NEXT: v_ldexp_f32 v2, v3, v5
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 32, v4
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v4, v5, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sitofp_v4i64_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_xor_b32_e32 v9, v0, v1
-; GFX9-NEXT: v_ffbh_i32_e32 v8, v1
+; GFX9-NEXT: v_xor_b32_e32 v9, v4, v5
+; GFX9-NEXT: v_ffbh_i32_e32 v8, v5
; GFX9-NEXT: v_ashrrev_i32_e32 v9, 31, v9
; GFX9-NEXT: v_add_u32_e32 v8, -1, v8
; GFX9-NEXT: v_add_u32_e32 v9, 32, v9
; GFX9-NEXT: v_min_u32_e32 v8, v8, v9
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
-; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX9-NEXT: v_sub_u32_e32 v8, 32, v8
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_xor_b32_e32 v5, v6, v7
+; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v4
+; GFX9-NEXT: v_ffbh_i32_e32 v4, v7
+; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v5
+; GFX9-NEXT: v_add_u32_e32 v4, -1, v4
+; GFX9-NEXT: v_add_u32_e32 v5, 32, v5
+; GFX9-NEXT: v_min_u32_e32 v10, v4, v5
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v10, v[6:7]
+; GFX9-NEXT: v_ldexp_f32 v6, v9, v8
+; GFX9-NEXT: v_xor_b32_e32 v8, v0, v1
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_ffbh_i32_e32 v7, v1
+; GFX9-NEXT: v_ashrrev_i32_e32 v8, 31, v8
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_add_u32_e32 v7, -1, v7
+; GFX9-NEXT: v_add_u32_e32 v8, 32, v8
+; GFX9-NEXT: v_cvt_f32_i32_e32 v4, v4
+; GFX9-NEXT: v_min_u32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX9-NEXT: v_sub_u32_e32 v5, 32, v10
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v9, v1, v0
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v0
; GFX9-NEXT: v_xor_b32_e32 v1, v2, v3
; GFX9-NEXT: v_ffbh_i32_e32 v0, v3
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v1
; GFX9-NEXT: v_add_u32_e32 v0, -1, v0
; GFX9-NEXT: v_add_u32_e32 v1, 32, v1
-; GFX9-NEXT: v_min_u32_e32 v10, v0, v1
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v10, v[2:3]
-; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v9
+; GFX9-NEXT: v_min_u32_e32 v8, v0, v1
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v5
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, 32, v8
-; GFX9-NEXT: v_ldexp_f32 v3, v2, v1
-; GFX9-NEXT: v_sub_u32_e32 v1, 32, v10
-; GFX9-NEXT: v_xor_b32_e32 v2, v4, v5
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_ffbh_i32_e32 v1, v5
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v2
-; GFX9-NEXT: v_add_u32_e32 v1, -1, v1
-; GFX9-NEXT: v_add_u32_e32 v2, 32, v2
-; GFX9-NEXT: v_min_u32_e32 v8, v1, v2
-; GFX9-NEXT: v_lshlrev_b64 v[1:2], v8, v[4:5]
-; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
-; GFX9-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v2, v1
-; GFX9-NEXT: v_xor_b32_e32 v2, v6, v7
-; GFX9-NEXT: v_ffbh_i32_e32 v1, v7
-; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v2
-; GFX9-NEXT: v_add_u32_e32 v1, -1, v1
-; GFX9-NEXT: v_add_u32_e32 v2, 32, v2
-; GFX9-NEXT: v_min_u32_e32 v4, v1, v2
-; GFX9-NEXT: v_lshlrev_b64 v[1:2], v4, v[6:7]
-; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX9-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, 32, v7
+; GFX9-NEXT: v_ldexp_f32 v1, v2, v1
; GFX9-NEXT: v_sub_u32_e32 v2, 32, v8
-; GFX9-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX9-NEXT: v_sub_u32_e32 v3, 32, v4
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v4, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_sitofp_v4i64_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_xor_b32_e32 v8, v0, v1
-; GFX10-NEXT: v_ffbh_i32_e32 v9, v1
-; GFX10-NEXT: v_ffbh_i32_e32 v10, v3
-; GFX10-NEXT: v_xor_b32_e32 v11, v2, v3
-; GFX10-NEXT: v_xor_b32_e32 v13, v4, v5
+; GFX10-NEXT: v_xor_b32_e32 v8, v4, v5
+; GFX10-NEXT: v_ffbh_i32_e32 v9, v5
+; GFX10-NEXT: v_xor_b32_e32 v11, v6, v7
+; GFX10-NEXT: v_xor_b32_e32 v13, v0, v1
+; GFX10-NEXT: v_xor_b32_e32 v14, v2, v3
; GFX10-NEXT: v_ashrrev_i32_e32 v8, 31, v8
; GFX10-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX10-NEXT: v_xor_b32_e32 v15, v6, v7
-; GFX10-NEXT: v_ffbh_i32_e32 v12, v5
-; GFX10-NEXT: v_ffbh_i32_e32 v14, v7
-; GFX10-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX10-NEXT: v_ffbh_i32_e32 v10, v7
+; GFX10-NEXT: v_ffbh_i32_e32 v12, v1
; GFX10-NEXT: v_ashrrev_i32_e32 v11, 31, v11
+; GFX10-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX10-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX10-NEXT: v_add_nc_u32_e32 v10, -1, v10
; GFX10-NEXT: v_add_nc_u32_e32 v12, -1, v12
-; GFX10-NEXT: v_add_nc_u32_e32 v14, -1, v14
-; GFX10-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX10-NEXT: v_add_nc_u32_e32 v9, -1, v10
-; GFX10-NEXT: v_ashrrev_i32_e32 v10, 31, v13
-; GFX10-NEXT: v_ashrrev_i32_e32 v13, 31, v15
; GFX10-NEXT: v_add_nc_u32_e32 v11, 32, v11
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
-; GFX10-NEXT: v_add_nc_u32_e32 v10, 32, v10
-; GFX10-NEXT: v_add_nc_u32_e32 v13, 32, v13
-; GFX10-NEXT: v_min_u32_e32 v9, v9, v11
+; GFX10-NEXT: v_min_u32_e32 v8, v9, v8
+; GFX10-NEXT: v_ashrrev_i32_e32 v9, 31, v13
+; GFX10-NEXT: v_ffbh_i32_e32 v13, v3
+; GFX10-NEXT: v_add_nc_u32_e32 v14, 32, v14
+; GFX10-NEXT: v_min_u32_e32 v10, v10, v11
+; GFX10-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX10-NEXT: v_add_nc_u32_e32 v9, 32, v9
+; GFX10-NEXT: v_add_nc_u32_e32 v13, -1, v13
+; GFX10-NEXT: v_lshlrev_b64 v[6:7], v10, v[6:7]
+; GFX10-NEXT: v_min_u32_e32 v9, v12, v9
+; GFX10-NEXT: v_min_u32_e32 v11, v13, v14
+; GFX10-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX10-NEXT: v_min_u32_e32 v6, 1, v6
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
+; GFX10-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX10-NEXT: v_or_b32_e32 v5, v7, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v11
; GFX10-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX10-NEXT: v_min_u32_e32 v10, v12, v10
-; GFX10-NEXT: v_min_u32_e32 v11, v14, v13
-; GFX10-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]
-; GFX10-NEXT: v_lshlrev_b64 v[6:7], v11, v[6:7]
; GFX10-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX10-NEXT: v_min_u32_e32 v1, 1, v4
-; GFX10-NEXT: v_min_u32_e32 v4, 1, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v7, 32, v10
+; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX10-NEXT: v_cvt_f32_i32_e32 v1, v4
; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v8
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v10
-; GFX10-NEXT: v_or_b32_e32 v1, v5, v1
-; GFX10-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX10-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX10-NEXT: v_cvt_f32_i32_e32 v4, v5
+; GFX10-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v5, 32, v9
-; GFX10-NEXT: v_sub_nc_u32_e32 v7, 32, v11
-; GFX10-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX10-NEXT: v_cvt_f32_i32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX10-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
; GFX10-NEXT: v_ldexp_f32 v3, v4, v7
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
; GFX10-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_sitofp_v4i64_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_xor_b32_e32 v8, v0, v1
-; GFX11-NEXT: v_cls_i32_e32 v9, v1
-; GFX11-NEXT: v_cls_i32_e32 v10, v3
-; GFX11-NEXT: v_xor_b32_e32 v11, v2, v3
-; GFX11-NEXT: v_xor_b32_e32 v13, v4, v5
+; GFX11-NEXT: v_xor_b32_e32 v8, v4, v5
+; GFX11-NEXT: v_cls_i32_e32 v9, v5
+; GFX11-NEXT: v_xor_b32_e32 v11, v6, v7
+; GFX11-NEXT: v_xor_b32_e32 v13, v0, v1
+; GFX11-NEXT: v_xor_b32_e32 v14, v2, v3
; GFX11-NEXT: v_ashrrev_i32_e32 v8, 31, v8
; GFX11-NEXT: v_add_nc_u32_e32 v9, -1, v9
-; GFX11-NEXT: v_xor_b32_e32 v15, v6, v7
-; GFX11-NEXT: v_cls_i32_e32 v12, v5
-; GFX11-NEXT: v_cls_i32_e32 v14, v7
-; GFX11-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_cls_i32_e32 v10, v7
+; GFX11-NEXT: v_cls_i32_e32 v12, v1
; GFX11-NEXT: v_ashrrev_i32_e32 v11, 31, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_add_nc_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_ashrrev_i32_e32 v14, 31, v14
+; GFX11-NEXT: v_add_nc_u32_e32 v10, -1, v10
; GFX11-NEXT: v_add_nc_u32_e32 v12, -1, v12
-; GFX11-NEXT: v_add_nc_u32_e32 v14, -1, v14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_min_u32_e32 v8, v9, v8
-; GFX11-NEXT: v_add_nc_u32_e32 v9, -1, v10
-; GFX11-NEXT: v_ashrrev_i32_e32 v10, 31, v13
-; GFX11-NEXT: v_ashrrev_i32_e32 v13, 31, v15
; GFX11-NEXT: v_add_nc_u32_e32 v11, 32, v11
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX11-NEXT: v_min_u32_e32 v8, v9, v8
+; GFX11-NEXT: v_ashrrev_i32_e32 v9, 31, v13
+; GFX11-NEXT: v_cls_i32_e32 v13, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v14, 32, v14
+; GFX11-NEXT: v_min_u32_e32 v10, v10, v11
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX11-NEXT: v_add_nc_u32_e32 v9, 32, v9
+; GFX11-NEXT: v_add_nc_u32_e32 v13, -1, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b64 v[6:7], v10, v[6:7]
+; GFX11-NEXT: v_min_u32_e32 v9, v12, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_min_u32_e32 v11, v13, v14
+; GFX11-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX11-NEXT: v_min_u32_e32 v6, 1, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_add_nc_u32_e32 v10, 32, v10
-; GFX11-NEXT: v_add_nc_u32_e32 v13, 32, v13
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v11, v[2:3]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_min_u32_e32 v9, v9, v11
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v11
; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_min_u32_e32 v10, v12, v10
-; GFX11-NEXT: v_min_u32_e32 v11, v14, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]
-; GFX11-NEXT: v_lshlrev_b64 v[6:7], v11, v[6:7]
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_min_u32_e32 v1, 1, v4
-; GFX11-NEXT: v_min_u32_e32 v4, 1, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_sub_nc_u32_e32 v7, 32, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v4
; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v8
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v1
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v5
+; GFX11-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v9
-; GFX11-NEXT: v_sub_nc_u32_e32 v7, 32, v11
-; GFX11-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX11-NEXT: v_cvt_f32_i32_e32 v4, v4
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v6
+; GFX11-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
; GFX11-NEXT: v_ldexp_f32 v3, v4, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11-NEXT: v_perm_b32 v1, v3, v1, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = sitofp <4 x i64> %x to <4 x bfloat>
ret <4 x bfloat> %op
@@ -23961,13 +23752,11 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v3i16_to_v3bf16:
@@ -23975,11 +23764,10 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX9-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX9-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uitofp_v3i16_to_v3bf16:
@@ -23987,29 +23775,10 @@ define <3 x bfloat> @v_uitofp_v3i16_to_v3bf16(<3 x i16> %x) {
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX10-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX10-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_uitofp_v3i16_to_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <3 x i16> %x to <3 x bfloat>
ret <3 x bfloat> %op
}
@@ -24052,55 +23821,55 @@ define <4 x bfloat> @v_uitofp_v4i16_to_v4bf16(<4 x i16> %x) {
; GFX8-LABEL: v_uitofp_v4i16_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+; GFX8-NEXT: v_cvt_f32_u32_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-; GFX8-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX8-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_alignbit_b32 v0, v3, v0, 16
; GFX8-NEXT: v_alignbit_b32 v1, v2, v1, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v4i16_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: v_cvt_f32_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX9-NEXT: v_cvt_f32_u32_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX9-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX9-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uitofp_v4i16_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_cvt_f32_u32_sdwa v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: v_cvt_f32_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+; GFX10-NEXT: v_cvt_f32_u32_sdwa v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_cvt_f32_u32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_cvt_f32_u32_sdwa v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
; GFX10-NEXT: v_cvt_f32_u32_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_uitofp_v4i16_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v1
+; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0
; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <4 x i16> %x to <4 x bfloat>
ret <4 x bfloat> %op
@@ -24236,12 +24005,12 @@ define <3 x bfloat> @v_uitofp_v3i32_to_v3bf16(<3 x i32> %x) {
; GFX8-LABEL: v_uitofp_v3i32_to_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v0, v1, v0, 16
+; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v1
+; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v3i32_to_v3bf16:
@@ -24298,22 +24067,22 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX8-LABEL: v_uitofp_v4i32_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX8-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX8-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v3
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v4i32_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
@@ -24323,9 +24092,9 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX10-LABEL: v_uitofp_v4i32_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX10-NEXT: v_cvt_f32_u32_e32 v3, v3
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
@@ -24334,11 +24103,11 @@ define <4 x bfloat> @v_uitofp_v4i32_to_v4bf16(<4 x i32> %x) {
; GFX11-LABEL: v_uitofp_v4i32_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -24653,65 +24422,65 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) {
; GFX8-LABEL: v_uitofp_v3i64_to_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ffbh_u32_e32 v6, v1
+; GFX8-NEXT: v_ffbh_u32_e32 v6, v5
; GFX8-NEXT: v_min_u32_e32 v6, 32, v6
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_f32_u32_e32 v7, v0
-; GFX8-NEXT: v_ffbh_u32_e32 v0, v3
-; GFX8-NEXT: v_min_u32_e32 v8, 32, v0
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cvt_f32_u32_e32 v4, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v6
+; GFX8-NEXT: v_ldexp_f32 v6, v4, v5
+; GFX8-NEXT: v_ffbh_u32_e32 v4, v1
+; GFX8-NEXT: v_min_u32_e32 v7, 32, v4
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v7, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v6
+; GFX8-NEXT: v_min_u32_e32 v0, 1, v4
+; GFX8-NEXT: v_ffbh_u32_e32 v4, v3
+; GFX8-NEXT: v_min_u32_e32 v4, 32, v4
+; GFX8-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]
+; GFX8-NEXT: v_or_b32_e32 v0, v5, v0
+; GFX8-NEXT: v_min_u32_e32 v2, 1, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 32, v8
-; GFX8-NEXT: v_ldexp_f32 v2, v7, v2
-; GFX8-NEXT: v_ldexp_f32 v3, v0, v1
-; GFX8-NEXT: v_ffbh_u32_e32 v0, v5
-; GFX8-NEXT: v_min_u32_e32 v6, 32, v0
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[4:5]
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v3, v2, 16
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 32, v4
+; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v7
+; GFX8-NEXT: v_ldexp_f32 v2, v2, v3
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v3i64_to_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_ffbh_u32_e32 v6, v5
+; GFX9-NEXT: v_min_u32_e32 v6, 32, v6
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v6, v[4:5]
+; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_sub_u32_e32 v5, 32, v6
; GFX9-NEXT: v_ffbh_u32_e32 v6, v1
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v4
; GFX9-NEXT: v_min_u32_e32 v6, 32, v6
; GFX9-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
-; GFX9-NEXT: v_sub_u32_e32 v6, 32, v6
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v0
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v0
; GFX9-NEXT: v_ffbh_u32_e32 v0, v3
-; GFX9-NEXT: v_min_u32_e32 v8, 32, v0
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
-; GFX9-NEXT: v_ldexp_f32 v2, v7, v6
-; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
-; GFX9-NEXT: v_ffbh_u32_e32 v0, v5
; GFX9-NEXT: v_min_u32_e32 v7, 32, v0
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[4:5]
-; GFX9-NEXT: v_sub_u32_e32 v6, 32, v8
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[2:3]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v5
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v0
-; GFX9-NEXT: v_ldexp_f32 v3, v3, v6
-; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v3, v2, s4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX9-NEXT: v_sub_u32_e32 v1, 32, v6
+; GFX9-NEXT: v_ldexp_f32 v1, v2, v1
; GFX9-NEXT: v_sub_u32_e32 v2, 32, v7
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v4, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uitofp_v3i64_to_v3bf16:
@@ -24726,21 +24495,21 @@ define <3 x bfloat> @v_uitofp_v3i64_to_v3bf16(<3 x i64> %x) {
; GFX10-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
; GFX10-NEXT: v_lshlrev_b64 v[2:3], v7, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v8, 32, v8
; GFX10-NEXT: v_min_u32_e32 v0, 1, v0
; GFX10-NEXT: v_min_u32_e32 v2, 1, v2
; GFX10-NEXT: v_min_u32_e32 v4, 1, v4
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: v_or_b32_e32 v1, v3, v2
; GFX10-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v7
-; GFX10-NEXT: v_sub_nc_u32_e32 v4, 32, v8
+; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v4, 32, v7
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v6
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX10-NEXT: v_ldexp_f32 v1, v1, v4
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v8
; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
; GFX10-NEXT: v_alignbit_b32 v1, s4, v2, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
@@ -24834,129 +24603,129 @@ define <4 x bfloat> @v_uitofp_v4i64_to_v4bf16(<4 x i64> %x) {
; GFX8-LABEL: v_uitofp_v4i64_to_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_ffbh_u32_e32 v8, v1
+; GFX8-NEXT: v_ffbh_u32_e32 v8, v5
; GFX8-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cvt_f32_u32_e32 v9, v4
+; GFX8-NEXT: v_ffbh_u32_e32 v4, v7
+; GFX8-NEXT: v_min_u32_e32 v10, 32, v4
+; GFX8-NEXT: v_lshlrev_b64 v[4:5], v10, v[6:7]
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 32, v8
+; GFX8-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_cvt_f32_u32_e32 v4, v4
+; GFX8-NEXT: v_ldexp_f32 v5, v9, v6
+; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 32, v10
+; GFX8-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX8-NEXT: v_ffbh_u32_e32 v6, v1
+; GFX8-NEXT: v_min_u32_e32 v6, 32, v6
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v6, v[0:1]
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT: v_cvt_f32_u32_e32 v9, v0
+; GFX8-NEXT: v_cvt_f32_u32_e32 v7, v0
; GFX8-NEXT: v_ffbh_u32_e32 v0, v3
-; GFX8-NEXT: v_min_u32_e32 v10, 32, v0
-; GFX8-NEXT: v_lshlrev_b64 v[0:1], v10, v[2:3]
-; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v8
+; GFX8-NEXT: v_min_u32_e32 v8, 32, v0
+; GFX8-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v6
; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 32, v10
-; GFX8-NEXT: v_ldexp_f32 v3, v9, v2
-; GFX8-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX8-NEXT: v_ffbh_u32_e32 v1, v5
-; GFX8-NEXT: v_min_u32_e32 v8, 32, v1
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v8, v[4:5]
+; GFX8-NEXT: v_ldexp_f32 v1, v7, v2
+; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v8
+; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
-; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v1
-; GFX8-NEXT: v_ffbh_u32_e32 v1, v7
-; GFX8-NEXT: v_min_u32_e32 v4, 32, v1
-; GFX8-NEXT: v_lshlrev_b64 v[1:2], v4, v[6:7]
-; GFX8-NEXT: v_sub_u32_e32 v5, vcc, 32, v8
-; GFX8-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX8-NEXT: v_ldexp_f32 v2, v3, v5
-; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 32, v4
-; GFX8-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v1, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v4, v5, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_uitofp_v4i64_to_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_ffbh_u32_e32 v8, v1
+; GFX9-NEXT: v_ffbh_u32_e32 v8, v5
; GFX9-NEXT: v_min_u32_e32 v8, 32, v8
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
-; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX9-NEXT: v_sub_u32_e32 v8, 32, v8
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v9, v4
+; GFX9-NEXT: v_ffbh_u32_e32 v4, v7
+; GFX9-NEXT: v_min_u32_e32 v10, 32, v4
+; GFX9-NEXT: v_lshlrev_b64 v[4:5], v10, v[6:7]
+; GFX9-NEXT: v_ffbh_u32_e32 v7, v1
+; GFX9-NEXT: v_min_u32_e32 v4, 1, v4
+; GFX9-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX9-NEXT: v_cvt_f32_u32_e32 v4, v4
+; GFX9-NEXT: v_min_u32_e32 v7, 32, v7
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v7, v[0:1]
+; GFX9-NEXT: v_sub_u32_e32 v5, 32, v10
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
-; GFX9-NEXT: v_or_b32_e32 v9, v1, v0
+; GFX9-NEXT: v_ldexp_f32 v4, v4, v5
+; GFX9-NEXT: v_or_b32_e32 v5, v1, v0
; GFX9-NEXT: v_ffbh_u32_e32 v0, v3
-; GFX9-NEXT: v_min_u32_e32 v10, 32, v0
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], v10, v[2:3]
-; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v9
+; GFX9-NEXT: v_ldexp_f32 v6, v9, v8
+; GFX9-NEXT: v_min_u32_e32 v8, 32, v0
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], v8, v[2:3]
+; GFX9-NEXT: v_cvt_f32_u32_e32 v2, v5
; GFX9-NEXT: v_min_u32_e32 v0, 1, v0
; GFX9-NEXT: v_or_b32_e32 v0, v1, v0
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX9-NEXT: v_sub_u32_e32 v1, 32, v8
-; GFX9-NEXT: v_ldexp_f32 v3, v2, v1
-; GFX9-NEXT: v_sub_u32_e32 v1, 32, v10
-; GFX9-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX9-NEXT: v_ffbh_u32_e32 v1, v5
-; GFX9-NEXT: v_min_u32_e32 v8, 32, v1
-; GFX9-NEXT: v_lshlrev_b64 v[1:2], v8, v[4:5]
-; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
-; GFX9-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v2, v1
-; GFX9-NEXT: v_ffbh_u32_e32 v1, v7
-; GFX9-NEXT: v_min_u32_e32 v4, 32, v1
-; GFX9-NEXT: v_lshlrev_b64 v[1:2], v4, v[6:7]
-; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v3
-; GFX9-NEXT: v_min_u32_e32 v1, 1, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX9-NEXT: v_sub_u32_e32 v1, 32, v7
+; GFX9-NEXT: v_ldexp_f32 v1, v2, v1
; GFX9-NEXT: v_sub_u32_e32 v2, 32, v8
-; GFX9-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX9-NEXT: v_sub_u32_e32 v3, 32, v4
-; GFX9-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_ldexp_f32 v0, v0, v2
+; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v4, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_uitofp_v4i64_to_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_ffbh_u32_e32 v8, v1
-; GFX10-NEXT: v_ffbh_u32_e32 v9, v3
-; GFX10-NEXT: v_ffbh_u32_e32 v10, v5
+; GFX10-NEXT: v_ffbh_u32_e32 v8, v5
+; GFX10-NEXT: v_ffbh_u32_e32 v9, v1
+; GFX10-NEXT: v_ffbh_u32_e32 v10, v3
; GFX10-NEXT: v_ffbh_u32_e32 v11, v7
; GFX10-NEXT: v_min_u32_e32 v8, 32, v8
; GFX10-NEXT: v_min_u32_e32 v9, 32, v9
; GFX10-NEXT: v_min_u32_e32 v10, 32, v10
; GFX10-NEXT: v_min_u32_e32 v11, 32, v11
-; GFX10-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
-; GFX10-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
-; GFX10-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]
+; GFX10-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX10-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
+; GFX10-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
; GFX10-NEXT: v_lshlrev_b64 v[6:7], v11, v[6:7]
; GFX10-NEXT: v_sub_nc_u32_e32 v8, 32, v8
+; GFX10-NEXT: v_min_u32_e32 v4, 1, v4
; GFX10-NEXT: v_min_u32_e32 v0, 1, v0
; GFX10-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX10-NEXT: v_min_u32_e32 v4, 1, v4
; GFX10-NEXT: v_min_u32_e32 v6, 1, v6
+; GFX10-NEXT: v_or_b32_e32 v4, v5, v4
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX10-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX10-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX10-NEXT: v_or_b32_e32 v4, v7, v6
-; GFX10-NEXT: v_sub_nc_u32_e32 v3, 32, v9
+; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX10-NEXT: v_or_b32_e32 v3, v7, v6
+; GFX10-NEXT: v_sub_nc_u32_e32 v1, 32, v11
+; GFX10-NEXT: v_cvt_f32_u32_e32 v4, v4
; GFX10-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX10-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX10-NEXT: v_sub_nc_u32_e32 v5, 32, v9
; GFX10-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX10-NEXT: v_sub_nc_u32_e32 v5, 32, v10
-; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v11
-; GFX10-NEXT: v_cvt_f32_u32_e32 v4, v4
-; GFX10-NEXT: v_ldexp_f32 v0, v0, v8
-; GFX10-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX10-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX10-NEXT: v_ldexp_f32 v3, v4, v6
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX10-NEXT: v_sub_nc_u32_e32 v6, 32, v10
+; GFX10-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX10-NEXT: v_ldexp_f32 v4, v4, v8
+; GFX10-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX10-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX10-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_uitofp_v4i64_to_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_clz_i32_u32_e32 v8, v1
-; GFX11-NEXT: v_clz_i32_u32_e32 v9, v3
-; GFX11-NEXT: v_clz_i32_u32_e32 v10, v5
+; GFX11-NEXT: v_clz_i32_u32_e32 v8, v5
+; GFX11-NEXT: v_clz_i32_u32_e32 v9, v1
+; GFX11-NEXT: v_clz_i32_u32_e32 v10, v3
; GFX11-NEXT: v_clz_i32_u32_e32 v11, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_min_u32_e32 v8, 32, v8
@@ -24965,37 +24734,37 @@ define <4 x bfloat> @v_uitofp_v4i64_to_v4bf16(<4 x i64> %x) {
; GFX11-NEXT: v_min_u32_e32 v10, 32, v10
; GFX11-NEXT: v_min_u32_e32 v11, 32, v11
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[0:1], v8, v[0:1]
-; GFX11-NEXT: v_lshlrev_b64 v[2:3], v9, v[2:3]
+; GFX11-NEXT: v_lshlrev_b64 v[4:5], v8, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[0:1], v9, v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_lshlrev_b64 v[4:5], v10, v[4:5]
+; GFX11-NEXT: v_lshlrev_b64 v[2:3], v10, v[2:3]
; GFX11-NEXT: v_lshlrev_b64 v[6:7], v11, v[6:7]
; GFX11-NEXT: v_sub_nc_u32_e32 v8, 32, v8
+; GFX11-NEXT: v_min_u32_e32 v4, 1, v4
; GFX11-NEXT: v_min_u32_e32 v0, 1, v0
; GFX11-NEXT: v_min_u32_e32 v2, 1, v2
-; GFX11-NEXT: v_min_u32_e32 v4, 1, v4
; GFX11-NEXT: v_min_u32_e32 v6, 1, v6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v6
-; GFX11-NEXT: v_sub_nc_u32_e32 v3, 32, v9
-; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
-; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v10
-; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v11
-; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v4
-; GFX11-NEXT: v_ldexp_f32 v0, v0, v8
-; GFX11-NEXT: v_ldexp_f32 v1, v1, v3
-; GFX11-NEXT: v_ldexp_f32 v2, v2, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_ldexp_f32 v3, v4, v6
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x7060302
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v6
+; GFX11-NEXT: v_sub_nc_u32_e32 v1, 32, v11
+; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v4
+; GFX11-NEXT: v_cvt_f32_u32_e32 v0, v0
+; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v9
+; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX11-NEXT: v_sub_nc_u32_e32 v6, 32, v10
+; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
+; GFX11-NEXT: v_ldexp_f32 v4, v4, v8
+; GFX11-NEXT: v_ldexp_f32 v0, v0, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_ldexp_f32 v2, v2, v6
+; GFX11-NEXT: v_ldexp_f32 v1, v3, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = uitofp <4 x i64> %x to <4 x bfloat>
ret <4 x bfloat> %op
@@ -25672,18 +25441,14 @@ define <3 x bfloat> @v_select_v3bf16(i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v3bf16:
@@ -25692,51 +25457,25 @@ define <3 x bfloat> @v_select_v3bf16(i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v3, v1, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v3bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v6, v5 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v3, v1, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v3, v1 :: v_dual_cndmask_b32 v1, v4, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b
ret <3 x bfloat> %op
@@ -25794,18 +25533,18 @@ define <4 x bfloat> @v_select_v4bf16(i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v4bf16:
@@ -25814,51 +25553,25 @@ define <4 x bfloat> @v_select_v4bf16(i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v4
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v3, v1, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v6, v5 :: v_dual_cndmask_b32 v2, v4, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v7, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v3, v1, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v3, v1 :: v_dual_cndmask_b32 v1, v4, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b
ret <4 x bfloat> %op
@@ -25932,24 +25645,24 @@ define <6 x bfloat> @v_select_v6bf16(i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v8, v7, vcc
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v6bf16:
@@ -25958,65 +25671,28 @@ define <6 x bfloat> @v_select_v6bf16(i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v6bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v6
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v10, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
-; GFX10-NEXT: v_perm_b32 v2, v5, v3, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v6bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v1 :: v_dual_cndmask_b32 v3, v6, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v5, v2 :: v_dual_cndmask_b32 v5, v10, v9
-; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v7 :: v_dual_cndmask_b32 v4, v8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v4, v2, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, v5, v3, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v1 :: v_dual_cndmask_b32 v1, v5, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc_lo
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <6 x bfloat> %a, <6 x bfloat> %b
ret <6 x bfloat> %op
@@ -26106,30 +25782,30 @@ define <8 x bfloat> @v_select_v8bf16(i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b)
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v7
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v9
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v8bf16:
@@ -26138,80 +25814,30 @@ define <8 x bfloat> @v_select_v8bf16(i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v6
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v8
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v5, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v2, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v2, v5, 0x5040100
-; GFX10-NEXT: v_perm_b32 v2, v6, v3, 0x5040100
-; GFX10-NEXT: v_perm_b32 v3, v7, v4, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v8, v4, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v8
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v5, v1 :: v_dual_cndmask_b32 v5, v6, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v7, v3 :: v_dual_cndmask_b32 v4, v8, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v7, v12, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc_lo
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v1, v2, v5, 0x5040100
-; GFX11-NEXT: v_perm_b32 v2, v6, v3, 0x5040100
-; GFX11-NEXT: v_perm_b32 v3, v7, v4, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v5, v1 :: v_dual_cndmask_b32 v1, v6, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v7, v3 :: v_dual_cndmask_b32 v3, v8, v4
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <8 x bfloat> %a, <8 x bfloat> %b
ret <8 x bfloat> %op
@@ -26373,54 +25999,54 @@ define <16 x bfloat> @v_select_v16bf16(i1 %cond, <16 x bfloat> %a, <16 x bfloat>
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v16, v16, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v15, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v14, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v13
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v14, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v12
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v13, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v12, v4, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v11
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v12, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v10, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v3, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v11
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v12, v4, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v13, v5, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v13
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v14, v6, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v7, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v16, v8, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v16
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v11
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v13
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v15
+; GFX8-NEXT: v_cndmask_b32_e32 v17, v18, v17, vcc
+; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v16
+; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v17
+; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v16bf16:
@@ -26429,140 +26055,40 @@ define <16 x bfloat> @v_select_v16bf16(i1 %cond, <16 x bfloat> %a, <16 x bfloat>
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v10, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v10
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v9, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v3, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v11
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v12, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v12
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v9, v4, vcc
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v13, v5, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v13
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
-; GFX9-NEXT: v_perm_b32 v4, v5, v4, s4
; GFX9-NEXT: v_cndmask_b32_e32 v5, v14, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v14
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v9, v6, vcc
-; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v7, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v15
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc
-; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
; GFX9-NEXT: v_cndmask_b32_e32 v7, v16, v8, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v16
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
-; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v16bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v9
-; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v10
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v18, v17, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v19, v0, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v11
-; GFX10-NEXT: v_perm_b32 v0, v9, v1, 0x5040100
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX10-NEXT: v_perm_b32 v1, v10, v2, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v9, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v10, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v11, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v18, v17, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v12
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
-; GFX10-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v10, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v17, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v14, v6, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v14
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v15
-; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v16
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v16, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v17, v14, vcc_lo
-; GFX10-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX10-NEXT: v_perm_b32 v4, v9, v5, 0x5040100
-; GFX10-NEXT: v_perm_b32 v5, v6, v10, 0x5040100
-; GFX10-NEXT: v_perm_b32 v6, v11, v7, 0x5040100
-; GFX10-NEXT: v_perm_b32 v7, v12, v8, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v13, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v14, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v16, v8, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v16bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v18, v17, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v10, v19, v0, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v11
-; GFX11-NEXT: v_perm_b32 v0, v9, v1, 0x5040100
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, v10, v2, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v2, v11, v3 :: v_dual_cndmask_b32 v3, v18, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v13
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v13, v5, vcc_lo
-; GFX11-NEXT: v_perm_b32 v2, v3, v2, 0x5040100
-; GFX11-NEXT: v_dual_cndmask_b32 v3, v12, v4 :: v_dual_cndmask_b32 v4, v10, v9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_dual_cndmask_b32 v9, v17, v11 :: v_dual_cndmask_b32 v10, v14, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v16
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v11, v6, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v7, v15, v7 :: v_dual_cndmask_b32 v8, v16, v8
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v13, v12, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-NEXT: v_cndmask_b32_e32 v12, v17, v14, vcc_lo
-; GFX11-NEXT: v_perm_b32 v3, v4, v3, 0x5040100
-; GFX11-NEXT: v_perm_b32 v4, v9, v5, 0x5040100
-; GFX11-NEXT: v_perm_b32 v5, v6, v10, 0x5040100
-; GFX11-NEXT: v_perm_b32 v6, v11, v7, 0x5040100
-; GFX11-NEXT: v_perm_b32 v7, v12, v8, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v9, v1 :: v_dual_cndmask_b32 v1, v10, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v11, v3 :: v_dual_cndmask_b32 v3, v12, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v13, v5 :: v_dual_cndmask_b32 v5, v14, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v15, v7 :: v_dual_cndmask_b32 v7, v16, v8
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <16 x bfloat> %a, <16 x bfloat> %b
ret <16 x bfloat> %op
@@ -26980,106 +26506,106 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat>
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v18, v2, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v18
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v19, v3, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v19
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v20, v4, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v20
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v21, v5, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v21
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc
-; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v22, v6, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v22
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v19, v6, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v23, v7, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v23
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v19, v7, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v24, v8, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v19, v8, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v25, v9, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v25
-; GFX8-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v9, v26, v10, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v26
-; GFX8-NEXT: v_cndmask_b32_e32 v10, v19, v10, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v10, v27, v11, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v27
-; GFX8-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_or_b32_sdwa v10, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v11, v28, v12, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v28
-; GFX8-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v12, v29, v13, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v29
-; GFX8-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v13, v30, v14, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v30
-; GFX8-NEXT: v_cndmask_b32_e32 v14, v19, v14, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v30
+; GFX8-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v30, 16, v29
+; GFX8-NEXT: v_cndmask_b32_e32 v30, v30, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v12
+; GFX8-NEXT: v_lshrrev_b32_e32 v29, 16, v28
+; GFX8-NEXT: v_cndmask_b32_e32 v29, v29, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v27
+; GFX8-NEXT: v_cndmask_b32_e32 v28, v28, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v26
+; GFX8-NEXT: v_cndmask_b32_e32 v27, v27, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v26, 16, v25
+; GFX8-NEXT: v_cndmask_b32_e32 v26, v26, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v24
+; GFX8-NEXT: v_cndmask_b32_e32 v25, v25, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v24, 16, v23
+; GFX8-NEXT: v_cndmask_b32_e32 v24, v24, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v22
+; GFX8-NEXT: v_cndmask_b32_e32 v23, v23, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v22, 16, v21
+; GFX8-NEXT: v_cndmask_b32_e32 v31, v32, v31, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v22, v22, v0, vcc
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32
+; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v20
; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_cndmask_b32_e32 v14, v17, v15, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v16, v0, v16, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v33, v0, v33, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v15
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v15, v18, v16, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v18
-; GFX8-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX8-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v32, v15, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; GFX8-NEXT: v_cndmask_b32_e32 v32, v32, v0, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v21, v21, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v19
+; GFX8-NEXT: v_cndmask_b32_e32 v20, v20, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v18
+; GFX8-NEXT: v_cndmask_b32_e32 v19, v19, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v17
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v19
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; GFX8-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v22
+; GFX8-NEXT: v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v23
+; GFX8-NEXT: v_or_b32_sdwa v5, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v24
+; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v25
+; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v26
+; GFX8-NEXT: v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v27
+; GFX8-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v28
+; GFX8-NEXT: v_or_b32_sdwa v10, v11, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v29
+; GFX8-NEXT: v_or_b32_sdwa v11, v12, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v30
+; GFX8-NEXT: v_or_b32_sdwa v12, v13, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v31
+; GFX8-NEXT: v_or_b32_sdwa v13, v14, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v32
+; GFX8-NEXT: v_or_b32_sdwa v14, v15, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v33
+; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_select_v32bf16:
@@ -27088,90 +26614,25 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat>
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v18, v2, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v18
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v17, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4
; GFX9-NEXT: v_cndmask_b32_e32 v2, v19, v3, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v19
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v17, v3, vcc
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
; GFX9-NEXT: v_cndmask_b32_e32 v3, v20, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v17, v4, vcc
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v21, v5, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v21
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v18, v5, vcc
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4
-; GFX9-NEXT: v_perm_b32 v4, v5, v4, s4
; GFX9-NEXT: v_cndmask_b32_e32 v5, v22, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v22
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v19, v6, vcc
-; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
; GFX9-NEXT: v_cndmask_b32_e32 v6, v23, v7, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v23
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v19, v7, vcc
-; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
; GFX9-NEXT: v_cndmask_b32_e32 v7, v24, v8, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v24
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v19, v8, vcc
-; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
; GFX9-NEXT: v_cndmask_b32_e32 v8, v25, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v25
-; GFX9-NEXT: v_cndmask_b32_e32 v9, v19, v9, vcc
-; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
; GFX9-NEXT: v_cndmask_b32_e32 v9, v26, v10, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v26
-; GFX9-NEXT: v_cndmask_b32_e32 v10, v19, v10, vcc
-; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
; GFX9-NEXT: v_cndmask_b32_e32 v10, v27, v11, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v27
-; GFX9-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc
-; GFX9-NEXT: v_perm_b32 v10, v11, v10, s4
; GFX9-NEXT: v_cndmask_b32_e32 v11, v28, v12, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v28
-; GFX9-NEXT: v_cndmask_b32_e32 v12, v19, v12, vcc
-; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
; GFX9-NEXT: v_cndmask_b32_e32 v12, v29, v13, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v29
-; GFX9-NEXT: v_cndmask_b32_e32 v13, v19, v13, vcc
-; GFX9-NEXT: v_perm_b32 v12, v13, v12, s4
; GFX9-NEXT: v_cndmask_b32_e32 v13, v30, v14, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v30
-; GFX9-NEXT: v_cndmask_b32_e32 v14, v19, v14, vcc
-; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_cndmask_b32_e32 v14, v17, v15, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc
-; GFX9-NEXT: v_perm_b32 v14, v15, v14, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cndmask_b32_e32 v15, v18, v16, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v18
-; GFX9-NEXT: v_cndmask_b32_e32 v16, v17, v16, vcc
-; GFX9-NEXT: v_perm_b32 v15, v16, v15, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_select_v32bf16:
@@ -27181,89 +26642,25 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat>
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v6
-; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v23
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v24
-; GFX10-NEXT: v_lshrrev_b32_e32 v65, 16, v9
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v25
-; GFX10-NEXT: v_lshrrev_b32_e32 v66, 16, v10
-; GFX10-NEXT: v_lshrrev_b32_e32 v67, 16, v26
-; GFX10-NEXT: v_lshrrev_b32_e32 v68, 16, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v27
-; GFX10-NEXT: v_cndmask_b32_e32 v33, v34, v33, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v35, v36, v35, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v37, v38, v37, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v20, v4, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v39, v48, v39, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v21, v5, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v49, v50, v49, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v22, v6, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v22, v52, v51, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v23, v7, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v23, v54, v53, vcc_lo
-; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v12
-; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v28
-; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v13
-; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v29
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v14
-; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v30
-; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v15
-; GFX10-NEXT: v_lshrrev_b32_e32 v21, 16, v16
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v24, v64, v55, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v25, v9, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v25, v0, v65, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v26, v10, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v26, v67, v66, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v27, v11, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v17, v17, v68, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v33, v1, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v35, v2, 0x5040100
-; GFX10-NEXT: v_perm_b32 v2, v37, v3, 0x5040100
-; GFX10-NEXT: v_perm_b32 v3, v39, v4, 0x5040100
-; GFX10-NEXT: v_perm_b32 v4, v49, v5, 0x5040100
-; GFX10-NEXT: v_perm_b32 v5, v22, v6, 0x5040100
-; GFX10-NEXT: v_perm_b32 v6, v23, v7, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v28, v12, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v18, v18, v34, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v29, v13, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v19, v19, v36, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v20, v20, v38, vcc_lo
-; GFX10-NEXT: v_perm_b32 v7, v24, v8, 0x5040100
-; GFX10-NEXT: v_perm_b32 v8, v25, v9, 0x5040100
-; GFX10-NEXT: v_perm_b32 v9, v26, v10, 0x5040100
-; GFX10-NEXT: v_perm_b32 v10, v17, v11, 0x5040100
-; GFX10-NEXT: v_perm_b32 v11, v18, v12, 0x5040100
-; GFX10-NEXT: v_perm_b32 v12, v19, v13, 0x5040100
-; GFX10-NEXT: v_perm_b32 v13, v20, v14, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v17, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v18, v2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v3, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v20, v4, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v21, v5, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v22, v6, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v23, v7, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v24, v8, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v25, v9, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v26, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v27, v11, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v28, v12, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v29, v13, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v30, v14, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v31
+; GFX10-NEXT: v_cndmask_b32_e32 v14, v31, v15, vcc_lo
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v32
-; GFX10-NEXT: v_cndmask_b32_e32 v15, v31, v15, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v16, v32, v16, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v17, v22, v48, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v21, v23, v21, vcc_lo
-; GFX10-NEXT: v_perm_b32 v14, v17, v15, 0x5040100
-; GFX10-NEXT: v_perm_b32 v15, v21, v16, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v32, v16, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_select_v32bf16:
@@ -27273,80 +26670,17 @@ define <32 x bfloat> @v_select_v32bf16(i1 %cond, <32 x bfloat> %a, <32 x bfloat>
; GFX11-NEXT: scratch_load_b32 v31, off, s32
; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v18
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v28
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v29
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v30
-; GFX11-NEXT: v_cndmask_b32_e32 v17, v34, v33, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v18, v36, v35, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v3
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v65, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v25
-; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v16
-; GFX11-NEXT: v_dual_cndmask_b32 v10, v26, v10 :: v_dual_cndmask_b32 v11, v27, v11
-; GFX11-NEXT: v_dual_cndmask_b32 v27, v70, v69 :: v_dual_cndmask_b32 v12, v28, v12
-; GFX11-NEXT: v_dual_cndmask_b32 v28, v80, v71 :: v_dual_cndmask_b32 v13, v29, v13
-; GFX11-NEXT: v_cndmask_b32_e32 v29, v82, v81, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v14, v30, v14, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v30, v0, v83, vcc_lo
-; GFX11-NEXT: v_perm_b32 v0, v17, v1, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v18, v2, 0x5040100
-; GFX11-NEXT: v_dual_cndmask_b32 v19, v38, v37 :: v_dual_cndmask_b32 v4, v20, v4
-; GFX11-NEXT: v_dual_cndmask_b32 v20, v48, v39 :: v_dual_cndmask_b32 v5, v21, v5
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v50, v49, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v6, v22, v6 :: v_dual_cndmask_b32 v7, v23, v7
-; GFX11-NEXT: v_dual_cndmask_b32 v22, v52, v51 :: v_dual_cndmask_b32 v23, v54, v53
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v24, v8, vcc_lo
-; GFX11-NEXT: v_dual_cndmask_b32 v24, v64, v55 :: v_dual_cndmask_b32 v9, v25, v9
-; GFX11-NEXT: v_dual_cndmask_b32 v25, v66, v65 :: v_dual_cndmask_b32 v26, v68, v67
-; GFX11-NEXT: v_perm_b32 v2, v19, v3, 0x5040100
-; GFX11-NEXT: v_perm_b32 v3, v20, v4, 0x5040100
-; GFX11-NEXT: v_perm_b32 v4, v21, v5, 0x5040100
-; GFX11-NEXT: v_perm_b32 v5, v22, v6, 0x5040100
-; GFX11-NEXT: v_perm_b32 v6, v23, v7, 0x5040100
-; GFX11-NEXT: v_perm_b32 v7, v24, v8, 0x5040100
-; GFX11-NEXT: v_perm_b32 v8, v25, v9, 0x5040100
-; GFX11-NEXT: v_perm_b32 v9, v26, v10, 0x5040100
-; GFX11-NEXT: v_perm_b32 v10, v27, v11, 0x5040100
-; GFX11-NEXT: v_perm_b32 v11, v28, v12, 0x5040100
-; GFX11-NEXT: v_perm_b32 v12, v29, v13, 0x5040100
-; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v31
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v17, v1 :: v_dual_cndmask_b32 v1, v18, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v19, v3 :: v_dual_cndmask_b32 v3, v20, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v21, v5 :: v_dual_cndmask_b32 v5, v22, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v23, v7 :: v_dual_cndmask_b32 v7, v24, v8
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v25, v9 :: v_dual_cndmask_b32 v9, v26, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v27, v11 :: v_dual_cndmask_b32 v11, v28, v12
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v29, v13 :: v_dual_cndmask_b32 v13, v30, v14
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v32
-; GFX11-NEXT: v_dual_cndmask_b32 v15, v31, v15 :: v_dual_cndmask_b32 v16, v32, v16
-; GFX11-NEXT: v_perm_b32 v13, v30, v14, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_cndmask_b32 v17, v17, v84 :: v_dual_cndmask_b32 v18, v18, v85
-; GFX11-NEXT: v_perm_b32 v14, v17, v15, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v15, v18, v16, 0x5040100
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v31, v15 :: v_dual_cndmask_b32 v15, v32, v16
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select i1 %cond, <32 x bfloat> %a, <32 x bfloat> %b
ret <32 x bfloat> %op
@@ -27413,10 +26747,17 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: s_lshr_b32 s0, s1, 16
+; GFX8-NEXT: s_lshr_b32 s2, s3, 16
; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v1, s3
-; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
@@ -27424,17 +26765,10 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
;
; GFX9-LABEL: s_select_v3bf16:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s4, s0, 16
-; GFX9-NEXT: s_lshr_b32 s5, s2, 16
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: s_mov_b32 s0, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s0
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
@@ -27445,39 +26779,28 @@ define amdgpu_ps <2 x i32> @s_select_v3bf16(<3 x bfloat> inreg %a, <3 x bfloat>
;
; GFX10-LABEL: s_select_v3bf16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s4, s0, 16
-; GFX10-NEXT: v_mov_b32_e32 v2, s0
-; GFX10-NEXT: v_mov_b32_e32 v1, s4
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, s1
-; GFX10-NEXT: s_lshr_b32 s5, s2, 16
-; GFX10-NEXT: v_cndmask_b32_e32 v2, s2, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, s3, v0, vcc_lo
-; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT: v_readfirstlane_b32 s0, v1
-; GFX10-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s2, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, s3, v2, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_select_v3bf16:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s0
-; GFX11-NEXT: v_mov_b32_e32 v0, s1
-; GFX11-NEXT: s_lshr_b32 s5, s2, 16
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v0, s3, v0, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x5040100
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s2, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, s3, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v1
-; GFX11-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-NEXT: ; return to shader part epilog
%cond = icmp eq i32 %c, 0
%op = select i1 %cond, <3 x bfloat> %a, <3 x bfloat> %b
@@ -27582,73 +26905,40 @@ define amdgpu_ps <2 x i32> @s_select_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX8-NEXT: v_readfirstlane_b32 s1, v0
; GFX8-NEXT: ; return to shader part epilog
;
-; GFX9-LABEL: s_select_v4bf16:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_lshr_b32 s4, s1, 16
-; GFX9-NEXT: s_lshr_b32 s5, s3, 16
-; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
-; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX9-LABEL: s_select_v4bf16:
+; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc
+; GFX9-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: s_mov_b32 s1, 0x5040100
-; GFX9-NEXT: s_lshr_b32 s3, s0, 16
-; GFX9-NEXT: s_lshr_b32 s4, s2, 16
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s1
-; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: v_mov_b32_e32 v2, s3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_mov_b32_e32 v2, s2
-; GFX9-NEXT: v_mov_b32_e32 v3, s0
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s1
; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: v_readfirstlane_b32 s1, v0
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_select_v4bf16:
; GFX10: ; %bb.0:
-; GFX10-NEXT: s_lshr_b32 s4, s1, 16
-; GFX10-NEXT: s_lshr_b32 s6, s0, 16
-; GFX10-NEXT: v_mov_b32_e32 v1, s4
-; GFX10-NEXT: v_mov_b32_e32 v2, s6
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX10-NEXT: v_mov_b32_e32 v0, s0
-; GFX10-NEXT: v_mov_b32_e32 v3, s1
-; GFX10-NEXT: s_lshr_b32 s5, s3, 16
-; GFX10-NEXT: s_lshr_b32 s0, s2, 16
-; GFX10-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e32 v3, s3, v3, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x5040100
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, s2, v2, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
; GFX10-NEXT: ; return to shader part epilog
;
; GFX11-LABEL: s_select_v4bf16:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-NEXT: s_lshr_b32 s6, s0, 16
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s6
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s1
-; GFX11-NEXT: s_lshr_b32 s5, s3, 16
-; GFX11-NEXT: s_lshr_b32 s0, s2, 16
-; GFX11-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v2, s0, v2, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
-; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v3, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x5040100
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v0, s3, v1, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v1, s2, v2, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: ; return to shader part epilog
%cond = icmp eq i32 %c, 0
%op = select i1 %cond, <4 x bfloat> %a, <4 x bfloat> %b
@@ -27887,96 +27177,95 @@ define <4 x bfloat> @v_vselect_v4bf16(<4 x i1> %cond, <4 x bfloat> %a, <4 x bflo
; GFX8-LABEL: v_vselect_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v8, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v6
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc
-; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_vselect_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v6
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v4, vcc
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v5, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v7
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v3, v2, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_vselect_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v4
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v6, v4, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v7
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc_lo
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_vselect_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v7, v5 :: v_dual_and_b32 v3, 1, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v4 :: v_dual_and_b32 v3, 1, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v6, v4 :: v_dual_and_b32 v1, 1, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v4, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v6, 16, v7
; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v6, v4, vcc_lo
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v7, v5, vcc_lo
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -28062,172 +27351,170 @@ define <8 x bfloat> @v_vselect_v8bf16(<8 x i1> %cond, <8 x bfloat> %a, <8 x bflo
; GFX8-LABEL: v_vselect_v8bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX8-NEXT: v_cndmask_b32_e32 v7, v17, v16, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v10
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v14
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_cndmask_b32_e32 v5, v15, v11, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v13
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v10, vcc
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v8
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v12
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX8-NEXT: v_cndmask_b32_e32 v1, v10, v9, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v12, v8, vcc
-; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v13, v9, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v13
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
-; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v14, v10, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v15, v11, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v11
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v15
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_vselect_v8bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
+; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v11, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v14
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v5, v11, v10, vcc
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v13
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v10, v9, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
; GFX9-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v12
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v12, v8, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v13, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v13
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v4
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v14, v10, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
-; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v15, v11, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v11
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v15
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v3, v2, s4
+; GFX9-NEXT: v_perm_b32 v2, v5, v4, s4
+; GFX9-NEXT: v_perm_b32 v3, v7, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_vselect_v8bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v10
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v14
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v8
-; GFX10-NEXT: v_lshrrev_b32_e32 v17, 16, v12
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v13
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
; GFX10-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v14
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v12, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v15
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v13, v9, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v14, v10, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v9, v8, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v11, vcc_lo
; GFX10-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v12, v10, vcc_lo
; GFX10-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_vselect_v8bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v14
+; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v15, v11 :: v_dual_and_b32 v1, 1, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v15
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v14, v10 :: v_dual_and_b32 v3, 1, v3
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v12
; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 16, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v17, v16, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v13, v9 :: v_dual_and_b32 v7, 1, v7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v12, v8 :: v_dual_and_b32 v7, 1, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v13
-; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v12, v8, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT: v_dual_cndmask_b32 v1, v17, v16 :: v_dual_and_b32 v6, 1, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v13, v9, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v14, v10, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v9, 16, v14
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v12, v8, vcc_lo
-; GFX11-NEXT: v_lshrrev_b32_e32 v12, 16, v15
-; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v8, 16, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v13, v9, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX11-NEXT: v_dual_cndmask_b32 v4, v14, v10 :: v_dual_and_b32 v5, 1, v5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v9, v8, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v15, v11, vcc_lo
; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v15, v11, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v12, v10, vcc_lo
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select <8 x i1> %cond, <8 x bfloat> %a, <8 x bfloat> %b
@@ -28469,244 +27756,259 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX8-LABEL: v_vselect_v16bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GFX8-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
+; GFX8-NEXT: s_mov_b64 exec, s[4:5]
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v1
; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
-; GFX8-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v1, s[4:5]
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v1, 1, v2
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX8-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v17
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v1, v25, v17, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v5
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v26
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
-; GFX8-NEXT: v_cndmask_b32_e32 v2, v26, v18, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_e32 v3, 1, v6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX8-NEXT: v_and_b32_e32 v3, 1, v7
-; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v3
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v5
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v6
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v7
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v8
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v9
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v10
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32
+; GFX8-NEXT: v_writelane_b32 v31, s30, 0
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v12
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v13
+; GFX8-NEXT: v_writelane_b32 v31, s31, 1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v2
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v22
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v30
+; GFX8-NEXT: v_writelane_b32 v31, s34, 2
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v11
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v14
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v15
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[28:29]
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v20
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v28
+; GFX8-NEXT: v_writelane_b32 v31, s35, 3
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v23
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v4
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v5
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v3, v2, s[20:21]
+; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v21
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v29
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v4, s[24:25]
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v19
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v27
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; GFX8-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX8-NEXT: v_cndmask_b32_e32 v3, v27, v19, vcc
-; GFX8-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX8-NEXT: v_and_b32_e32 v5, 1, v11
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v4, v28, v20, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v28
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
-; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v29, v21, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v21
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v29
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
-; GFX8-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX8-NEXT: v_cndmask_b32_e32 v5, v10, v9, vcc
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v27
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v9, v4, s[16:17]
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v24
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v30, v22, s[26:27]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v27, v19, s[14:15]
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v29, v21, s[22:23]
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v28, v20, s[18:19]
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v26, v18, s[10:11]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v25, v17, s[6:7]
+; GFX8-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v10
; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX8-NEXT: v_or_b32_sdwa v6, v7, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v4, v11, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_sdwa v5, v8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v30, v22, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v22
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v30
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc
-; GFX8-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
-; GFX8-NEXT: v_or_b32_sdwa v6, v8, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v23
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v8, v7, v23, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
-; GFX8-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v0, v23, s[30:31]
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v2, v1, s[34:35]
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v18
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v26
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v1, v0, s[12:13]
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v25
+; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v0, s[8:9]
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e64 v0, v15, v0, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v15, v24, v16, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v13
+; GFX8-NEXT: v_or_b32_sdwa v0, v15, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v1, v14, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v2, v9, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v7, v12, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_readlane_b32 s35, v31, 3
+; GFX8-NEXT: v_readlane_b32 s34, v31, 2
+; GFX8-NEXT: v_readlane_b32 s31, v31, 1
+; GFX8-NEXT: v_readlane_b32 s30, v31, 0
+; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
+; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
+; GFX8-NEXT: s_mov_b64 exec, s[4:5]
+; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_vselect_v16bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v14
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 1, v15
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v4
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32
+; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX9-NEXT: v_and_b32_e32 v12, 1, v13
+; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v10
+; GFX9-NEXT: v_and_b32_e32 v10, 1, v11
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v6
+; GFX9-NEXT: v_and_b32_e32 v6, 1, v7
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v22
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v30
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v10
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v8
+; GFX9-NEXT: v_and_b32_e32 v8, 1, v9
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v5, s[4:5]
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v21
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v29
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v9, v5, s[8:9]
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v28
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, v9, s[12:13]
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v19
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v27
+; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v13, v11, s[16:17]
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v23
+; GFX9-NEXT: v_cndmask_b32_e32 v6, v30, v22, vcc
+; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v26, v18, s[18:19]
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v29, v21, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v28, v20, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v27, v19, s[14:15]
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v5, v5, v8, s4
+; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v4, v23, s[20:21]
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v4, v13, s[22:23]
+; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v26
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v18, v4, s[24:25]
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v25
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v18, v17, vcc
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
-; GFX9-NEXT: v_and_b32_e32 v0, 1, v1
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v24
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v16, v1, s[4:5]
-; GFX9-NEXT: s_mov_b32 s6, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s6
-; GFX9-NEXT: v_and_b32_e32 v1, 1, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v24
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
-; GFX9-NEXT: v_and_b32_e32 v1, 1, v3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v25
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v25, v17, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[4:5]
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s6
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v4
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v5
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v26
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v26, v18, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s6
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v6
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v3
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v7
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v27
-; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX9-NEXT: v_cndmask_b32_e32 v3, v27, v19, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; GFX9-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v8
-; GFX9-NEXT: v_and_b32_e32 v5, 1, v11
-; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v4, v28, v20, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v20
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v28
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v9
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v11, v8, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v10
-; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX9-NEXT: v_perm_b32 v4, v8, v4, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v29, v21, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v21
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v29
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v13
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v10, v9, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v12
-; GFX9-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX9-NEXT: v_perm_b32 v5, v5, v8, s6
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v30, v22, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v22
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v30
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v6
-; GFX9-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v9, vcc
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v14
-; GFX9-NEXT: v_perm_b32 v6, v6, v8, s6
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v23
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v8, v7, v23, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v15
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
-; GFX9-NEXT: v_perm_b32 v7, v7, v8, s6
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v16, vcc
+; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4
+; GFX9-NEXT: v_perm_b32 v1, v3, v2, s4
+; GFX9-NEXT: v_perm_b32 v2, v4, v15, s4
+; GFX9-NEXT: v_perm_b32 v3, v11, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v9, v10, s4
+; GFX9-NEXT: v_perm_b32 v7, v13, v14, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_vselect_v16bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v22
+; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v30
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v29
+; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v28
+; GFX10-NEXT: v_cndmask_b32_e32 v13, v34, v33, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v24
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX10-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
+; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v17
+; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v25
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v18
-; GFX10-NEXT: v_lshrrev_b32_e32 v37, 16, v26
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v16
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v24
; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v19
-; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v27
-; GFX10-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v28
-; GFX10-NEXT: v_cndmask_b32_e32 v3, v35, v34, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v21
-; GFX10-NEXT: v_lshrrev_b32_e32 v51, 16, v29
-; GFX10-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v26
; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v22
-; GFX10-NEXT: v_lshrrev_b32_e32 v53, 16, v30
-; GFX10-NEXT: v_cndmask_b32_e32 v5, v37, v36, vcc_lo
+; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v19
+; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v27
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
; GFX10-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v23
-; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
+; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v23
; GFX10-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v26, v18, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v52, v51, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v54, v53, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
+; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v50, v49, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX10-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX10-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v39, v38, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; GFX10-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; GFX10-NEXT: v_cndmask_b32_e32 v9, v49, v48, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v48, v39, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX10-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
-; GFX10-NEXT: v_cndmask_b32_e32 v11, v51, v50, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX10-NEXT: v_perm_b32 v5, v11, v10, 0x5040100
-; GFX10-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
-; GFX10-NEXT: v_cndmask_b32_e32 v13, v53, v52, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v31
; GFX10-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
-; GFX10-NEXT: v_cndmask_b32_e32 v15, v3, v54, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v15, v3, v32, vcc_lo
; GFX10-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX10-NEXT: v_perm_b32 v6, v13, v12, 0x5040100
; GFX10-NEXT: v_perm_b32 v7, v15, v14, 0x5040100
@@ -28716,78 +28018,79 @@ define <16 x bfloat> @v_vselect_v16bf16(<16 x i1> %cond, <16 x bfloat> %a, <16 x
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v23
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v27
+; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v18
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v22
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v26
+; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v30, v22 :: v_dual_and_b32 v11, 1, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v16
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v34, v33, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v24
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT: v_dual_cndmask_b32 v0, v24, v16 :: v_dual_and_b32 v3, 1, v3
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v25
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v21
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v33, v32, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v29
-; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v17
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v36, v35, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v26
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v20
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v35, v34, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v25
; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v38, v37, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
; GFX11-NEXT: v_dual_cndmask_b32 v4, v26, v18 :: v_dual_and_b32 v7, 1, v7
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v25, v17, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v52, v51, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v24, v16, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v54, v53, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v27
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v37, v36, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v50, v49, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v27, v19, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
-; GFX11-NEXT: v_dual_cndmask_b32 v7, v39, v38 :: v_dual_and_b32 v8, 1, v8
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v28, v20, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v49, v48, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v48, v39, vcc_lo
; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v10, v29, v21, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v51, v50, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v12, v30, v22, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
-; GFX11-NEXT: v_cndmask_b32_e32 v13, v53, v52, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v31
+; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11-NEXT: v_cndmask_b32_e32 v14, v31, v23, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_cndmask_b32_e32 v15, v3, v54, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v3, v32, vcc_lo
; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
; GFX11-NEXT: v_perm_b32 v6, v13, v12, 0x5040100
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v7, v15, v14, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select <16 x i1> %cond, <16 x bfloat> %a, <16 x bfloat> %b
@@ -29252,171 +28555,235 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_writelane_b32 v31, s30, 0
; GFX8-NEXT: v_writelane_b32 v31, s31, 1
; GFX8-NEXT: v_writelane_b32 v31, s34, 2
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_writelane_b32 v31, s35, 3
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v1
; GFX8-NEXT: v_writelane_b32 v31, s36, 4
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
; GFX8-NEXT: v_writelane_b32 v31, s37, 5
-; GFX8-NEXT: v_and_b32_e32 v21, 1, v21
-; GFX8-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v3
; GFX8-NEXT: v_writelane_b32 v31, s38, 6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18
-; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68
-; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4
-; GFX8-NEXT: v_and_b32_e32 v17, 1, v17
-; GFX8-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v4
; GFX8-NEXT: v_writelane_b32 v31, s39, 7
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16
-; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8
-; GFX8-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v5
; GFX8-NEXT: v_writelane_b32 v31, s40, 8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14
-; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76
-; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v6
; GFX8-NEXT: v_writelane_b32 v31, s41, 9
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v7
; GFX8-NEXT: v_writelane_b32 v31, s42, 10
-; GFX8-NEXT: v_and_b32_e32 v13, 1, v13
-; GFX8-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v8
; GFX8-NEXT: v_writelane_b32 v31, s43, 11
-; GFX8-NEXT: v_and_b32_e32 v20, 1, v20
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12
-; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80
-; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20
-; GFX8-NEXT: buffer_load_ushort v20, off, s[0:3], s32
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v9
; GFX8-NEXT: v_writelane_b32 v31, s44, 12
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v10
; GFX8-NEXT: v_writelane_b32 v31, s45, 13
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v11
; GFX8-NEXT: v_writelane_b32 v31, s46, 14
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v12
; GFX8-NEXT: v_writelane_b32 v31, s47, 15
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v13
; GFX8-NEXT: v_writelane_b32 v31, s48, 16
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v14
; GFX8-NEXT: v_writelane_b32 v31, s49, 17
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v15
; GFX8-NEXT: v_writelane_b32 v31, s50, 18
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v16
; GFX8-NEXT: v_writelane_b32 v31, s51, 19
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v17
; GFX8-NEXT: v_writelane_b32 v31, s52, 20
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v18
; GFX8-NEXT: v_writelane_b32 v31, s53, 21
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v19
; GFX8-NEXT: v_writelane_b32 v31, s54, 22
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v20
; GFX8-NEXT: v_writelane_b32 v31, s55, 23
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v21
; GFX8-NEXT: v_writelane_b32 v31, s56, 24
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v22
; GFX8-NEXT: v_writelane_b32 v31, s57, 25
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v23
; GFX8-NEXT: v_writelane_b32 v31, s58, 26
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v24
; GFX8-NEXT: v_writelane_b32 v31, s59, 27
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v25
; GFX8-NEXT: v_writelane_b32 v31, s60, 28
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v26
; GFX8-NEXT: v_writelane_b32 v31, s61, 29
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v27
; GFX8-NEXT: v_writelane_b32 v31, s62, 30
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v28
; GFX8-NEXT: v_writelane_b32 v31, s63, 31
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v29
; GFX8-NEXT: v_writelane_b32 v31, s64, 32
-; GFX8-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX8-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v30
; GFX8-NEXT: v_writelane_b32 v31, s65, 33
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7
-; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:84
-; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:20
-; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0
+; GFX8-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX8-NEXT: v_writelane_b32 v31, s66, 34
-; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1
-; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_writelane_b32 v31, s67, 35
-; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4
-; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:88
-; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:24
-; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX8-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX8-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9
-; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:92
-; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:28
-; GFX8-NEXT: v_and_b32_e32 v25, 1, v25
-; GFX8-NEXT: v_and_b32_e32 v24, 1, v24
-; GFX8-NEXT: v_and_b32_e32 v23, 1, v23
-; GFX8-NEXT: v_and_b32_e32 v22, 1, v22
-; GFX8-NEXT: v_and_b32_e32 v19, 1, v19
-; GFX8-NEXT: s_waitcnt vmcnt(14)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; GFX8-NEXT: s_waitcnt vmcnt(13)
-; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v21
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65]
-; GFX8-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67]
-; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: s_waitcnt vmcnt(13)
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; GFX8-NEXT: s_waitcnt vmcnt(12)
-; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v17
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61]
-; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63]
-; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68
+; GFX8-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; GFX8-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72
+; GFX8-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
+; GFX8-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76
+; GFX8-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; GFX8-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80
+; GFX8-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16
+; GFX8-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84
+; GFX8-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
+; GFX8-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88
+; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24
+; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92
+; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28
+; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96
+; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32
+; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100
+; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36
+; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104
+; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40
+; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108
; GFX8-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44
-; GFX8-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56
-; GFX8-NEXT: s_waitcnt vmcnt(13)
-; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v15
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v14
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[56:57]
-; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59]
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX8-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: s_waitcnt vmcnt(11)
-; GFX8-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55]
-; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v13
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11
-; GFX8-NEXT: s_waitcnt vmcnt(10)
-; GFX8-NEXT: v_and_b32_e32 v11, 1, v20
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[52:53]
-; GFX8-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128
-; GFX8-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11
-; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112
-; GFX8-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:108
-; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
-; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32
-; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:104
-; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:100
-; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX8-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120
-; GFX8-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124
-; GFX8-NEXT: v_and_b32_e32 v26, 1, v26
-; GFX8-NEXT: v_and_b32_e32 v28, 1, v28
-; GFX8-NEXT: v_and_b32_e32 v27, 1, v27
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26
-; GFX8-NEXT: v_and_b32_e32 v29, 1, v29
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27
-; GFX8-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29
-; GFX8-NEXT: v_and_b32_e32 v30, 1, v30
-; GFX8-NEXT: s_waitcnt vmcnt(14)
-; GFX8-NEXT: v_cndmask_b32_e64 v4, v7, v8, s[50:51]
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[48:49]
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30
+; GFX8-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112
+; GFX8-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48
+; GFX8-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116
+; GFX8-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52
+; GFX8-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
+; GFX8-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56
+; GFX8-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:124
+; GFX8-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60
+; GFX8-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:128
+; GFX8-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v29
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b32_e32 v28, 16, v33
+; GFX8-NEXT: v_cndmask_b32_e64 v28, v34, v28, s[66:67]
+; GFX8-NEXT: v_cndmask_b32_e64 v29, v29, v33, s[64:65]
+; GFX8-NEXT: v_lshrrev_b32_e32 v33, 16, v32
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v30
+; GFX8-NEXT: v_cndmask_b32_e64 v33, v34, v33, s[62:63]
+; GFX8-NEXT: v_cndmask_b32_e64 v30, v30, v32, s[60:61]
+; GFX8-NEXT: v_lshrrev_b32_e32 v32, 16, v27
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v26
+; GFX8-NEXT: v_cndmask_b32_e64 v32, v34, v32, s[58:59]
+; GFX8-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57]
+; GFX8-NEXT: v_lshrrev_b32_e32 v27, 16, v25
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v24
+; GFX8-NEXT: v_cndmask_b32_e64 v27, v34, v27, s[54:55]
+; GFX8-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53]
+; GFX8-NEXT: v_lshrrev_b32_e32 v25, 16, v23
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v22
+; GFX8-NEXT: v_cndmask_b32_e64 v25, v34, v25, s[50:51]
+; GFX8-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49]
+; GFX8-NEXT: v_lshrrev_b32_e32 v23, 16, v21
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v20
+; GFX8-NEXT: v_cndmask_b32_e64 v23, v34, v23, s[46:47]
+; GFX8-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45]
+; GFX8-NEXT: v_lshrrev_b32_e32 v21, 16, v19
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v18
+; GFX8-NEXT: v_cndmask_b32_e64 v21, v34, v21, s[42:43]
+; GFX8-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41]
+; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v17
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v16
+; GFX8-NEXT: v_cndmask_b32_e64 v19, v34, v19, s[38:39]
+; GFX8-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37]
+; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v15
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v14
+; GFX8-NEXT: v_cndmask_b32_e64 v17, v34, v17, s[34:35]
+; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31]
+; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v13
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v12
+; GFX8-NEXT: v_cndmask_b32_e64 v15, v34, v15, s[28:29]
+; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27]
+; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v11
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v10
+; GFX8-NEXT: v_cndmask_b32_e64 v13, v34, v13, s[24:25]
+; GFX8-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23]
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v9
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v8
+; GFX8-NEXT: v_cndmask_b32_e64 v11, v34, v11, s[20:21]
+; GFX8-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19]
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v7
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v6
+; GFX8-NEXT: v_cndmask_b32_e64 v9, v34, v9, s[16:17]
+; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15]
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v4
+; GFX8-NEXT: v_cndmask_b32_e64 v7, v34, v7, s[12:13]
+; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11]
+; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v2
+; GFX8-NEXT: v_cndmask_b32_e64 v5, v34, v5, s[8:9]
+; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7]
+; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v34, 16, v0
+; GFX8-NEXT: v_cndmask_b32_e64 v3, v34, v3, s[4:5]
+; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v5
+; GFX8-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v9
+; GFX8-NEXT: v_or_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v13
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v15
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v17
+; GFX8-NEXT: v_or_b32_sdwa v4, v8, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v7, v14, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v19
+; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v23
+; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v25
+; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v27
+; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v32
+; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v33
+; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v28
+; GFX8-NEXT: v_or_b32_sdwa v8, v16, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v9, v18, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v11, v22, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v12, v24, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v13, v26, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v14, v30, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX8-NEXT: v_or_b32_sdwa v15, v29, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_readlane_b32 s67, v31, 35
; GFX8-NEXT: v_readlane_b32 s66, v31, 34
; GFX8-NEXT: v_readlane_b32 s65, v31, 33
@@ -29427,18 +28794,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_readlane_b32 s60, v31, 28
; GFX8-NEXT: v_readlane_b32 s59, v31, 27
; GFX8-NEXT: v_readlane_b32 s58, v31, 26
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v5, v6, s[46:47]
-; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[44:45]
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX8-NEXT: v_or_b32_sdwa v5, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v10
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v9
-; GFX8-NEXT: v_cndmask_b32_e64 v6, v9, v10, s[42:43]
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41]
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX8-NEXT: v_or_b32_sdwa v6, v6, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_readlane_b32 s57, v31, 25
; GFX8-NEXT: v_readlane_b32 s56, v31, 24
; GFX8-NEXT: v_readlane_b32 s55, v31, 23
@@ -29457,43 +28812,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_readlane_b32 s42, v31, 10
; GFX8-NEXT: v_readlane_b32 s41, v31, 9
; GFX8-NEXT: v_readlane_b32 s40, v31, 8
-; GFX8-NEXT: s_waitcnt vmcnt(6)
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v22
-; GFX8-NEXT: s_waitcnt vmcnt(5)
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v23
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37]
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v18
-; GFX8-NEXT: s_waitcnt vmcnt(3)
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v25
-; GFX8-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39]
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v10, v9, s[30:31]
-; GFX8-NEXT: v_or_b32_sdwa v7, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e64 v8, v25, v18, s[34:35]
-; GFX8-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX8-NEXT: v_or_b32_sdwa v8, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e64 v9, v24, v16, s[28:29]
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v24
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v16, v10, s[26:27]
-; GFX8-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
-; GFX8-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX8-NEXT: v_or_b32_sdwa v9, v9, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_cndmask_b32_e64 v10, v11, v21, s[24:25]
-; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v21
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[22:23]
-; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60
-; GFX8-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX8-NEXT: v_or_b32_sdwa v10, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: s_waitcnt vmcnt(4)
-; GFX8-NEXT: v_cndmask_b32_e64 v11, v19, v20, s[20:21]
-; GFX8-NEXT: v_lshrrev_b32_e32 v20, 16, v20
-; GFX8-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17]
-; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64
-; GFX8-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX8-NEXT: v_or_b32_sdwa v11, v11, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: v_readlane_b32 s39, v31, 7
; GFX8-NEXT: v_readlane_b32 s38, v31, 6
; GFX8-NEXT: v_readlane_b32 s37, v31, 5
@@ -29502,33 +28820,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX8-NEXT: v_readlane_b32 s34, v31, 2
; GFX8-NEXT: v_readlane_b32 s31, v31, 1
; GFX8-NEXT: v_readlane_b32 s30, v31, 0
-; GFX8-NEXT: s_waitcnt vmcnt(2)
-; GFX8-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15]
-; GFX8-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13]
-; GFX8-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11]
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9]
-; GFX8-NEXT: s_waitcnt vmcnt(1)
-; GFX8-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7]
-; GFX8-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX8-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; GFX8-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX8-NEXT: v_or_b32_sdwa v14, v17, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc
-; GFX8-NEXT: v_lshrrev_b32_e32 v17, 16, v20
-; GFX8-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19]
-; GFX8-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX8-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX8-NEXT: v_or_b32_sdwa v12, v19, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_sdwa v13, v18, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT: v_or_b32_sdwa v15, v16, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX8-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX8-NEXT: s_mov_b64 exec, s[4:5]
@@ -29544,169 +28835,223 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX9-NEXT: v_writelane_b32 v31, s30, 0
; GFX9-NEXT: v_writelane_b32 v31, s31, 1
; GFX9-NEXT: v_writelane_b32 v31, s34, 2
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_writelane_b32 v31, s35, 3
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v3
; GFX9-NEXT: v_writelane_b32 v31, s36, 4
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v2
; GFX9-NEXT: v_writelane_b32 v31, s37, 5
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v5
; GFX9-NEXT: v_writelane_b32 v31, s38, 6
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v4
; GFX9-NEXT: v_writelane_b32 v31, s39, 7
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v7
; GFX9-NEXT: v_writelane_b32 v31, s40, 8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v6
; GFX9-NEXT: v_writelane_b32 v31, s41, 9
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v9
; GFX9-NEXT: v_writelane_b32 v31, s42, 10
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v8
; GFX9-NEXT: v_writelane_b32 v31, s43, 11
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v11
; GFX9-NEXT: v_writelane_b32 v31, s44, 12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v10
; GFX9-NEXT: v_writelane_b32 v31, s45, 13
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v13
; GFX9-NEXT: v_writelane_b32 v31, s46, 14
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v12
; GFX9-NEXT: v_writelane_b32 v31, s47, 15
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v15
; GFX9-NEXT: v_writelane_b32 v31, s48, 16
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v14
; GFX9-NEXT: v_writelane_b32 v31, s49, 17
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v17
; GFX9-NEXT: v_writelane_b32 v31, s50, 18
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v16
; GFX9-NEXT: v_writelane_b32 v31, s51, 19
-; GFX9-NEXT: v_and_b32_e32 v21, 1, v21
-; GFX9-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v19
; GFX9-NEXT: v_writelane_b32 v31, s52, 20
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[22:23], 1, v21
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[28:29], 1, v18
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:4
-; GFX9-NEXT: v_and_b32_e32 v17, 1, v17
-; GFX9-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v18
; GFX9-NEXT: v_writelane_b32 v31, s53, 21
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[30:31], 1, v17
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[34:35], 1, v16
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:8
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v21
; GFX9-NEXT: v_writelane_b32 v31, s54, 22
-; GFX9-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX9-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v20
; GFX9-NEXT: v_writelane_b32 v31, s55, 23
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[36:37], 1, v15
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[38:39], 1, v14
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:76
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v23
; GFX9-NEXT: v_writelane_b32 v31, s56, 24
-; GFX9-NEXT: v_and_b32_e32 v13, 1, v13
-; GFX9-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v22
; GFX9-NEXT: v_writelane_b32 v31, s57, 25
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[40:41], 1, v13
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[42:43], 1, v12
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:16
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v25
; GFX9-NEXT: v_writelane_b32 v31, s58, 26
-; GFX9-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v24
; GFX9-NEXT: v_writelane_b32 v31, s59, 27
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v5
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:20
-; GFX9-NEXT: v_and_b32_e32 v20, 1, v20
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[24:25], 1, v20
-; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v27
; GFX9-NEXT: v_writelane_b32 v31, s60, 28
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[56:57], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v26
; GFX9-NEXT: v_writelane_b32 v31, s61, 29
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[58:59], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v29
; GFX9-NEXT: v_writelane_b32 v31, s62, 30
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v28
; GFX9-NEXT: v_writelane_b32 v31, s63, 31
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v0
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32
; GFX9-NEXT: v_writelane_b32 v31, s64, 32
; GFX9-NEXT: v_writelane_b32 v31, s65, 33
; GFX9-NEXT: v_writelane_b32 v31, s66, 34
-; GFX9-NEXT: v_and_b32_e32 v2, 1, v2
; GFX9-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_writelane_b32 v31, s67, 35
-; GFX9-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[62:63], 1, v2
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v1
+; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX9-NEXT: v_cmp_eq_u32_e64 s[64:65], 1, v0
+; GFX9-NEXT: v_and_b32_e32 v0, 1, v30
; GFX9-NEXT: v_cmp_eq_u32_e64 s[66:67], 1, v0
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[60:61], 1, v3
-; GFX9-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX9-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[54:55], 1, v6
-; GFX9-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[52:53], 1, v7
-; GFX9-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[50:51], 1, v8
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[48:49], 1, v9
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:24
-; GFX9-NEXT: v_and_b32_e32 v24, 1, v24
-; GFX9-NEXT: v_and_b32_e32 v11, 1, v11
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[14:15], 1, v24
-; GFX9-NEXT: v_and_b32_e32 v23, 1, v23
-; GFX9-NEXT: v_and_b32_e32 v22, 1, v22
-; GFX9-NEXT: v_and_b32_e32 v19, 1, v19
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[44:45], 1, v11
-; GFX9-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:48
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[16:17], 1, v23
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[20:21], 1, v22
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[26:27], 1, v19
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[46:47], 1, v10
-; GFX9-NEXT: v_and_b32_e32 v26, 1, v26
-; GFX9-NEXT: v_and_b32_e32 v25, 1, v25
-; GFX9-NEXT: v_and_b32_e32 v28, 1, v28
-; GFX9-NEXT: v_and_b32_e32 v27, 1, v27
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[10:11], 1, v26
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[12:13], 1, v25
-; GFX9-NEXT: v_and_b32_e32 v29, 1, v29
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[6:7], 1, v28
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[8:9], 1, v27
-; GFX9-NEXT: v_and_b32_e32 v30, 1, v30
-; GFX9-NEXT: s_waitcnt vmcnt(13)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v18
-; GFX9-NEXT: s_waitcnt vmcnt(12)
-; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v21
-; GFX9-NEXT: v_cndmask_b32_e64 v0, v18, v21, s[66:67]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[64:65]
-; GFX9-NEXT: s_mov_b32 s64, 0x5040100
-; GFX9-NEXT: v_perm_b32 v0, v1, v0, s64
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v16
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_cndmask_b32_e64 v1, v16, v17, s[62:63]
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[60:61]
-; GFX9-NEXT: v_perm_b32 v1, v2, v1, s64
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:88
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:104
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:108
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_cndmask_b32_e64 v2, v14, v15, s[58:59]
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v15
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:120
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:64
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_cndmask_b32_e64 v29, v32, v33, s[66:67]
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v33
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v32
+; GFX9-NEXT: v_cndmask_b32_e64 v32, v32, v33, s[64:65]
+; GFX9-NEXT: v_cndmask_b32_e64 v33, v28, v30, s[62:63]
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; GFX9-NEXT: v_cndmask_b32_e64 v28, v28, v30, s[60:61]
+; GFX9-NEXT: v_cndmask_b32_e64 v30, v26, v27, s[58:59]
+; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; GFX9-NEXT: v_cndmask_b32_e64 v26, v26, v27, s[56:57]
+; GFX9-NEXT: v_cndmask_b32_e64 v27, v24, v25, s[54:55]
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; GFX9-NEXT: v_cndmask_b32_e64 v24, v24, v25, s[52:53]
+; GFX9-NEXT: v_cndmask_b32_e64 v25, v22, v23, s[50:51]
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; GFX9-NEXT: v_cndmask_b32_e64 v22, v22, v23, s[48:49]
+; GFX9-NEXT: v_cndmask_b32_e64 v23, v20, v21, s[46:47]
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v21
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; GFX9-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[44:45]
+; GFX9-NEXT: v_cndmask_b32_e64 v21, v18, v19, s[42:43]
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_cndmask_b32_e64 v18, v18, v19, s[40:41]
+; GFX9-NEXT: v_cndmask_b32_e64 v19, v16, v17, s[38:39]
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_cndmask_b32_e64 v16, v16, v17, s[36:37]
+; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v15, s[34:35]
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v14, v3, s[56:57]
-; GFX9-NEXT: v_perm_b32 v2, v3, v2, s64
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:124
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:128
-; GFX9-NEXT: s_waitcnt vmcnt(11)
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v12, v13, s[54:55]
+; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v15, s[30:31]
+; GFX9-NEXT: v_cndmask_b32_e64 v15, v12, v13, s[28:29]
; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[52:53]
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:120
-; GFX9-NEXT: v_perm_b32 v3, v12, v3, s64
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], 1, v29
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v4, v5, s[50:51]
+; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v13, s[26:27]
+; GFX9-NEXT: v_cndmask_b32_e64 v13, v10, v11, s[24:25]
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[22:23]
+; GFX9-NEXT: v_cndmask_b32_e64 v11, v8, v9, s[20:21]
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[18:19]
+; GFX9-NEXT: v_cndmask_b32_e64 v9, v6, v7, s[16:17]
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[14:15]
+; GFX9-NEXT: v_cndmask_b32_e64 v7, v4, v5, s[12:13]
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[48:49]
-; GFX9-NEXT: v_perm_b32 v4, v4, v12, s64
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:116
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_and_b32_e32 v11, 1, v20
-; GFX9-NEXT: v_cmp_eq_u32_e64 s[18:19], 1, v11
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:92
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:32
-; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v30
+; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[10:11]
+; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, v3, s[8:9]
+; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[6:7]
+; GFX9-NEXT: v_cndmask_b32_e64 v3, v0, v1, s[4:5]
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
+; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v5, s4
+; GFX9-NEXT: v_perm_b32 v2, v4, v7, s4
+; GFX9-NEXT: v_perm_b32 v3, v6, v9, s4
+; GFX9-NEXT: v_perm_b32 v4, v8, v11, s4
+; GFX9-NEXT: v_perm_b32 v5, v10, v13, s4
+; GFX9-NEXT: v_perm_b32 v6, v12, v15, s4
+; GFX9-NEXT: v_perm_b32 v7, v14, v17, s4
+; GFX9-NEXT: v_perm_b32 v8, v16, v19, s4
+; GFX9-NEXT: v_perm_b32 v9, v18, v21, s4
+; GFX9-NEXT: v_perm_b32 v10, v20, v23, s4
+; GFX9-NEXT: v_perm_b32 v11, v22, v25, s4
+; GFX9-NEXT: v_perm_b32 v12, v24, v27, s4
+; GFX9-NEXT: v_perm_b32 v13, v26, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v28, v33, s4
+; GFX9-NEXT: v_perm_b32 v15, v32, v29, s4
; GFX9-NEXT: v_readlane_b32 s67, v31, 35
; GFX9-NEXT: v_readlane_b32 s66, v31, 34
; GFX9-NEXT: v_readlane_b32 s65, v31, 33
+; GFX9-NEXT: v_readlane_b32 s64, v31, 32
; GFX9-NEXT: v_readlane_b32 s63, v31, 31
; GFX9-NEXT: v_readlane_b32 s62, v31, 30
; GFX9-NEXT: v_readlane_b32 s61, v31, 29
@@ -29722,54 +29067,11 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX9-NEXT: v_readlane_b32 s51, v31, 19
; GFX9-NEXT: v_readlane_b32 s50, v31, 18
; GFX9-NEXT: v_readlane_b32 s49, v31, 17
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v7, s[46:47]
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[44:45]
-; GFX9-NEXT: v_perm_b32 v5, v6, v5, s64
; GFX9-NEXT: v_readlane_b32 s48, v31, 16
; GFX9-NEXT: v_readlane_b32 s47, v31, 15
; GFX9-NEXT: v_readlane_b32 s46, v31, 14
; GFX9-NEXT: v_readlane_b32 s45, v31, 13
; GFX9-NEXT: v_readlane_b32 s44, v31, 12
-; GFX9-NEXT: s_waitcnt vmcnt(6)
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v9, s[42:43]
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v8, v7, s[40:41]
-; GFX9-NEXT: v_perm_b32 v6, v7, v6, s64
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v22
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v23
-; GFX9-NEXT: v_cndmask_b32_e64 v7, v22, v23, s[38:39]
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v9, v8, s[36:37]
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20
-; GFX9-NEXT: v_perm_b32 v7, v8, v7, s64
-; GFX9-NEXT: v_cndmask_b32_e64 v8, v20, v18, s[34:35]
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v17, v9, s[30:31]
-; GFX9-NEXT: v_perm_b32 v8, v9, v8, s64
-; GFX9-NEXT: v_cndmask_b32_e64 v9, v11, v16, s[28:29]
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:56
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[26:27]
-; GFX9-NEXT: v_perm_b32 v9, v11, v9, s64
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v10, v21, s[24:25]
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v21
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_cndmask_b32_e64 v10, v10, v16, s[22:23]
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:60
-; GFX9-NEXT: v_perm_b32 v10, v10, v11, s64
-; GFX9-NEXT: v_cndmask_b32_e64 v11, v19, v24, s[20:21]
-; GFX9-NEXT: v_lshrrev_b32_e32 v20, 16, v24
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v19
-; GFX9-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[16:17]
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64
-; GFX9-NEXT: v_perm_b32 v11, v19, v11, s64
; GFX9-NEXT: v_readlane_b32 s43, v31, 11
; GFX9-NEXT: v_readlane_b32 s42, v31, 10
; GFX9-NEXT: v_readlane_b32 s41, v31, 9
@@ -29782,31 +29084,6 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX9-NEXT: v_readlane_b32 s34, v31, 2
; GFX9-NEXT: v_readlane_b32 s31, v31, 1
; GFX9-NEXT: v_readlane_b32 s30, v31, 0
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_cndmask_b32_e64 v19, v12, v18, s[14:15]
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_cndmask_b32_e64 v12, v12, v18, s[12:13]
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_cndmask_b32_e64 v18, v13, v17, s[10:11]
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[8:9]
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_cndmask_b32_e64 v17, v14, v16, s[6:7]
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; GFX9-NEXT: v_perm_b32 v14, v14, v17, s64
-; GFX9-NEXT: v_perm_b32 v12, v12, v19, s64
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cndmask_b32_e32 v16, v15, v20, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v20
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[18:19]
-; GFX9-NEXT: v_perm_b32 v13, v13, v18, s64
-; GFX9-NEXT: v_perm_b32 v15, v15, v16, s64
-; GFX9-NEXT: v_readlane_b32 s64, v31, 32
; GFX9-NEXT: s_xor_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
@@ -29820,205 +29097,208 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX10-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4
-; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
-; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 1, v6
-; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
-; GFX10-NEXT: v_and_b32_e32 v16, 1, v16
-; GFX10-NEXT: s_clause 0x15
-; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:68
-; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:4
-; GFX10-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:72
-; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:8
-; GFX10-NEXT: buffer_load_ushort v36, off, s[0:3], s32
-; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:76
-; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:12
-; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:80
-; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:16
-; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:20
-; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:84
-; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:88
-; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:24
-; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:92
-; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:28
-; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:96
-; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:32
-; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:36
-; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:104
-; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:40
-; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:100
-; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:52
-; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v0
-; GFX10-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:112
-; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v2
-; GFX10-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:48
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v4
-; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120
-; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v3
-; GFX10-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56
-; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v8
-; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116
-; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108
-; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v10
-; GFX10-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124
-; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v12
-; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:60
-; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v14
-; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:128
-; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v16
-; GFX10-NEXT: s_clause 0x1
-; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:64
-; GFX10-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:44
-; GFX10-NEXT: v_writelane_b32 v31, s30, 0
+; GFX10-NEXT: v_and_b32_e32 v29, 1, v29
; GFX10-NEXT: v_and_b32_e32 v30, 1, v30
; GFX10-NEXT: v_and_b32_e32 v28, 1, v28
; GFX10-NEXT: v_and_b32_e32 v26, 1, v26
; GFX10-NEXT: v_and_b32_e32 v24, 1, v24
-; GFX10-NEXT: v_writelane_b32 v31, s31, 1
; GFX10-NEXT: v_and_b32_e32 v22, 1, v22
; GFX10-NEXT: v_and_b32_e32 v20, 1, v20
-; GFX10-NEXT: v_and_b32_e32 v17, 1, v17
-; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
-; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT: v_writelane_b32 v31, s34, 2
-; GFX10-NEXT: v_and_b32_e32 v29, 1, v29
-; GFX10-NEXT: v_and_b32_e32 v27, 1, v27
-; GFX10-NEXT: v_and_b32_e32 v25, 1, v25
-; GFX10-NEXT: v_and_b32_e32 v23, 1, v23
-; GFX10-NEXT: v_and_b32_e32 v21, 1, v21
-; GFX10-NEXT: v_and_b32_e32 v19, 1, v19
; GFX10-NEXT: v_and_b32_e32 v18, 1, v18
-; GFX10-NEXT: v_and_b32_e32 v15, 1, v15
-; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
-; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX10-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX10-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX10-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX10-NEXT: s_clause 0x14
+; GFX10-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:60
+; GFX10-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:124
+; GFX10-NEXT: buffer_load_ushort v34, off, s[0:3], s32
+; GFX10-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:128
+; GFX10-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:64
+; GFX10-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:48
+; GFX10-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:116
+; GFX10-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:52
+; GFX10-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:120
+; GFX10-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:56
+; GFX10-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:32
+; GFX10-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:100
+; GFX10-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:36
+; GFX10-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:104
+; GFX10-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:40
+; GFX10-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:108
+; GFX10-NEXT: buffer_load_dword v64, off, s[0:3], s32 offset:44
+; GFX10-NEXT: buffer_load_dword v65, off, s[0:3], s32 offset:112
+; GFX10-NEXT: buffer_load_dword v66, off, s[0:3], s32 offset:72
+; GFX10-NEXT: buffer_load_dword v67, off, s[0:3], s32 offset:76
+; GFX10-NEXT: buffer_load_dword v68, off, s[0:3], s32 offset:80
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:92
+; GFX10-NEXT: buffer_load_dword v69, off, s[0:3], s32 offset:28
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v30
+; GFX10-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:96
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 1, v28
+; GFX10-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:88
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 1, v26
+; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 1, v24
+; GFX10-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:84
+; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 1, v22
+; GFX10-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:20
+; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 1, v20
+; GFX10-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 1, v18
+; GFX10-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:12
+; GFX10-NEXT: v_cmp_eq_u32_e64 s11, 1, v16
+; GFX10-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:8
+; GFX10-NEXT: v_cmp_eq_u32_e64 s12, 1, v14
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:68
+; GFX10-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:24
+; GFX10-NEXT: v_cmp_eq_u32_e64 s13, 1, v12
+; GFX10-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:4
+; GFX10-NEXT: v_writelane_b32 v31, s30, 0
+; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX10-NEXT: v_writelane_b32 v31, s31, 1
+; GFX10-NEXT: v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX10-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX10-NEXT: v_writelane_b32 v31, s34, 2
; GFX10-NEXT: v_and_b32_e32 v5, 1, v5
-; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v20
-; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v22
-; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v24
-; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v26
-; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v28
-; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v30
-; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v7
-; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v9
-; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v17
+; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX10-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX10-NEXT: v_and_b32_e32 v11, 1, v11
+; GFX10-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX10-NEXT: v_and_b32_e32 v15, 1, v15
+; GFX10-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX10-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX10-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX10-NEXT: v_and_b32_e32 v23, 1, v23
+; GFX10-NEXT: v_and_b32_e32 v25, 1, v25
+; GFX10-NEXT: v_and_b32_e32 v27, 1, v27
+; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v10
+; GFX10-NEXT: v_cmp_eq_u32_e64 s15, 1, v8
+; GFX10-NEXT: v_cmp_eq_u32_e64 s16, 1, v6
+; GFX10-NEXT: v_cmp_eq_u32_e64 s17, 1, v4
+; GFX10-NEXT: v_cmp_eq_u32_e64 s18, 1, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s19, 1, v0
; GFX10-NEXT: v_writelane_b32 v31, s35, 3
-; GFX10-NEXT: v_cmp_eq_u32_e64 s14, 1, v18
-; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v5
-; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v11
-; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s20, 1, v27
+; GFX10-NEXT: v_cmp_eq_u32_e64 s21, 1, v25
+; GFX10-NEXT: v_cmp_eq_u32_e64 s22, 1, v23
+; GFX10-NEXT: v_cmp_eq_u32_e64 s23, 1, v21
+; GFX10-NEXT: v_cmp_eq_u32_e64 s24, 1, v19
+; GFX10-NEXT: v_cmp_eq_u32_e64 s25, 1, v17
; GFX10-NEXT: v_cmp_eq_u32_e64 s26, 1, v15
-; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v19
-; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v21
-; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v23
-; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v25
-; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v27
-; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v29
+; GFX10-NEXT: v_cmp_eq_u32_e64 s27, 1, v13
+; GFX10-NEXT: v_cmp_eq_u32_e64 s28, 1, v11
+; GFX10-NEXT: v_cmp_eq_u32_e64 s29, 1, v7
+; GFX10-NEXT: v_cmp_eq_u32_e64 s30, 1, v3
+; GFX10-NEXT: v_cmp_eq_u32_e64 s31, 1, v1
+; GFX10-NEXT: v_cmp_eq_u32_e64 s34, 1, v5
+; GFX10-NEXT: v_cmp_eq_u32_e64 s35, 1, v9
; GFX10-NEXT: s_waitcnt vmcnt(32)
-; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v32
+; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v32
; GFX10-NEXT: s_waitcnt vmcnt(31)
-; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v33
-; GFX10-NEXT: v_cndmask_b32_e64 v5, v32, v33, s4
+; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v33
+; GFX10-NEXT: s_waitcnt vmcnt(30)
+; GFX10-NEXT: v_and_b32_e32 v2, 1, v34
; GFX10-NEXT: s_waitcnt vmcnt(29)
-; GFX10-NEXT: v_cndmask_b32_e64 v11, v34, v35, s5
+; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v35
; GFX10-NEXT: s_waitcnt vmcnt(28)
-; GFX10-NEXT: v_and_b32_e32 v17, 1, v36
-; GFX10-NEXT: v_lshrrev_b32_e32 v13, 16, v35
-; GFX10-NEXT: v_lshrrev_b32_e32 v15, 16, v34
-; GFX10-NEXT: s_waitcnt vmcnt(26)
-; GFX10-NEXT: v_cndmask_b32_e64 v18, v37, v38, s7
-; GFX10-NEXT: v_lshrrev_b32_e32 v19, 16, v38
-; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v37
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v35, v36, s4
+; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v36
+; GFX10-NEXT: v_cndmask_b32_e64 v17, v33, v32, s5
+; GFX10-NEXT: s_waitcnt vmcnt(25)
+; GFX10-NEXT: v_cndmask_b32_e64 v19, v38, v39, s7
; GFX10-NEXT: s_waitcnt vmcnt(24)
-; GFX10-NEXT: v_cndmask_b32_e64 v21, v39, v48, s8
-; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v48
-; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v39
-; GFX10-NEXT: s_waitcnt vmcnt(22)
-; GFX10-NEXT: v_cndmask_b32_e64 v24, v50, v49, s9
-; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v49
-; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v50
-; GFX10-NEXT: s_waitcnt vmcnt(20)
-; GFX10-NEXT: v_cndmask_b32_e64 v27, v51, v52, s10
-; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v52
-; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v51
+; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v48
+; GFX10-NEXT: s_waitcnt vmcnt(23)
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v48, v49, s6
+; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v49
+; GFX10-NEXT: v_lshrrev_b32_e32 v7, 16, v39
+; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v38
+; GFX10-NEXT: v_lshrrev_b32_e32 v9, 16, v37
; GFX10-NEXT: s_waitcnt vmcnt(18)
-; GFX10-NEXT: v_cndmask_b32_e64 v30, v53, v54, s11
+; GFX10-NEXT: v_cndmask_b32_e64 v27, v53, v54, s10
+; GFX10-NEXT: s_waitcnt vmcnt(17)
+; GFX10-NEXT: v_lshrrev_b32_e32 v25, 16, v55
+; GFX10-NEXT: s_waitcnt vmcnt(16)
+; GFX10-NEXT: v_cndmask_b32_e64 v21, v55, v64, s9
+; GFX10-NEXT: s_waitcnt vmcnt(15)
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v65, v37, s8
+; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v65
+; GFX10-NEXT: v_lshrrev_b32_e32 v23, 16, v64
; GFX10-NEXT: v_lshrrev_b32_e32 v32, 16, v54
; GFX10-NEXT: v_lshrrev_b32_e32 v33, 16, v53
-; GFX10-NEXT: s_waitcnt vmcnt(16)
-; GFX10-NEXT: v_cndmask_b32_e64 v34, v55, v64, s12
-; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v64
-; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v55
-; GFX10-NEXT: s_waitcnt vmcnt(12)
-; GFX10-NEXT: v_cndmask_b32_e64 v37, v68, v65, s13
-; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v65
-; GFX10-NEXT: v_lshrrev_b32_e32 v39, 16, v68
-; GFX10-NEXT: v_lshrrev_b32_e32 v49, 16, v67
-; GFX10-NEXT: v_lshrrev_b32_e32 v50, 16, v66
+; GFX10-NEXT: v_cndmask_b32_e64 v34, v51, v52, s11
+; GFX10-NEXT: v_lshrrev_b32_e32 v35, 16, v52
+; GFX10-NEXT: v_lshrrev_b32_e32 v36, 16, v51
; GFX10-NEXT: s_waitcnt vmcnt(9)
-; GFX10-NEXT: v_cndmask_b32_e64 v52, v0, v2, s16
-; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX10-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v37, v30, v50, s12
+; GFX10-NEXT: v_lshrrev_b32_e32 v38, 16, v50
+; GFX10-NEXT: v_lshrrev_b32_e32 v30, 16, v30
+; GFX10-NEXT: v_cndmask_b32_e64 v39, v29, v69, s13
+; GFX10-NEXT: v_lshrrev_b32_e32 v48, 16, v69
+; GFX10-NEXT: v_lshrrev_b32_e32 v29, 16, v29
; GFX10-NEXT: s_waitcnt vmcnt(6)
-; GFX10-NEXT: v_cndmask_b32_e64 v53, v8, v69, s17
-; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v69
-; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v8
-; GFX10-NEXT: v_cndmask_b32_e64 v55, v4, v3, s18
-; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX10-NEXT: v_lshrrev_b32_e32 v4, 16, v4
-; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_cndmask_b32_e64 v64, v10, v12, s19
-; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12
-; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cndmask_b32_e64 v51, v1, v6, s15
-; GFX10-NEXT: v_lshrrev_b32_e32 v6, 16, v6
-; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX10-NEXT: v_lshrrev_b32_e32 v10, 16, v10
-; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v16, s20
+; GFX10-NEXT: v_cndmask_b32_e64 v50, v24, v22, s15
+; GFX10-NEXT: v_lshrrev_b32_e32 v22, 16, v22
+; GFX10-NEXT: v_lshrrev_b32_e32 v24, 16, v24
+; GFX10-NEXT: s_waitcnt vmcnt(5)
+; GFX10-NEXT: v_cndmask_b32_e64 v51, v68, v20, s16
+; GFX10-NEXT: v_lshrrev_b32_e32 v20, 16, v20
+; GFX10-NEXT: v_lshrrev_b32_e32 v52, 16, v68
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_cndmask_b32_e64 v53, v67, v18, s17
+; GFX10-NEXT: v_lshrrev_b32_e32 v18, 16, v18
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_cndmask_b32_e64 v49, v28, v26, s14
+; GFX10-NEXT: v_lshrrev_b32_e32 v26, 16, v26
+; GFX10-NEXT: v_lshrrev_b32_e32 v28, 16, v28
+; GFX10-NEXT: v_lshrrev_b32_e32 v54, 16, v67
+; GFX10-NEXT: v_cndmask_b32_e64 v55, v66, v16, s18
; GFX10-NEXT: v_lshrrev_b32_e32 v16, 16, v16
+; GFX10-NEXT: v_lshrrev_b32_e32 v64, 16, v66
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_cndmask_b32_e64 v65, v14, v12, s19
+; GFX10-NEXT: v_lshrrev_b32_e32 v12, 16, v12
; GFX10-NEXT: v_lshrrev_b32_e32 v14, 16, v14
-; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v7, vcc_lo
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17
-; GFX10-NEXT: v_cndmask_b32_e64 v48, v66, v67, s14
-; GFX10-NEXT: v_cndmask_b32_e64 v9, v15, v13, s6
-; GFX10-NEXT: v_cndmask_b32_e64 v13, v20, v19, s21
-; GFX10-NEXT: v_cndmask_b32_e64 v15, v23, v22, s22
-; GFX10-NEXT: v_cndmask_b32_e64 v19, v26, v25, s23
-; GFX10-NEXT: v_cndmask_b32_e64 v20, v29, v28, s24
-; GFX10-NEXT: v_cndmask_b32_e64 v22, v33, v32, s25
-; GFX10-NEXT: v_cndmask_b32_e64 v23, v36, v35, s26
-; GFX10-NEXT: v_cndmask_b32_e64 v25, v39, v38, s27
-; GFX10-NEXT: v_cndmask_b32_e64 v26, v50, v49, s28
-; GFX10-NEXT: v_cndmask_b32_e64 v28, v1, v6, s29
-; GFX10-NEXT: v_cndmask_b32_e64 v17, v0, v2, s30
-; GFX10-NEXT: v_cndmask_b32_e64 v29, v8, v54, s31
-; GFX10-NEXT: v_cndmask_b32_e64 v32, v4, v3, s34
-; GFX10-NEXT: v_cndmask_b32_e64 v33, v10, v12, s35
-; GFX10-NEXT: v_cndmask_b32_e32 v16, v14, v16, vcc_lo
-; GFX10-NEXT: v_perm_b32 v0, v7, v5, 0x5040100
-; GFX10-NEXT: v_perm_b32 v1, v9, v11, 0x5040100
-; GFX10-NEXT: v_perm_b32 v2, v13, v18, 0x5040100
-; GFX10-NEXT: v_perm_b32 v3, v15, v21, 0x5040100
-; GFX10-NEXT: v_perm_b32 v4, v19, v24, 0x5040100
-; GFX10-NEXT: v_perm_b32 v5, v20, v27, 0x5040100
-; GFX10-NEXT: v_perm_b32 v6, v22, v30, 0x5040100
-; GFX10-NEXT: v_perm_b32 v7, v23, v34, 0x5040100
-; GFX10-NEXT: v_perm_b32 v8, v25, v37, 0x5040100
-; GFX10-NEXT: v_perm_b32 v9, v26, v48, 0x5040100
-; GFX10-NEXT: v_perm_b32 v10, v28, v51, 0x5040100
-; GFX10-NEXT: v_perm_b32 v11, v17, v52, 0x5040100
-; GFX10-NEXT: v_perm_b32 v12, v29, v53, 0x5040100
-; GFX10-NEXT: v_perm_b32 v13, v32, v55, 0x5040100
-; GFX10-NEXT: v_perm_b32 v14, v33, v64, 0x5040100
-; GFX10-NEXT: v_perm_b32 v15, v16, v65, 0x5040100
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v66, v1, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v67, v6, v5, s20
+; GFX10-NEXT: v_cndmask_b32_e64 v68, v8, v7, s21
+; GFX10-NEXT: v_cndmask_b32_e64 v69, v10, v9, s22
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v25, v23, s23
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v33, v32, s24
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v36, v35, s25
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v30, v38, s26
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v29, v48, s27
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v28, v26, s28
+; GFX10-NEXT: v_cndmask_b32_e64 v20, v52, v20, s29
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v14, v12, s31
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v64, v16, s30
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v54, v18, s34
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v24, v22, s35
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v4, v3, s4
+; GFX10-NEXT: v_perm_b32 v0, v0, v65, 0x5040100
+; GFX10-NEXT: v_perm_b32 v1, v1, v55, 0x5040100
+; GFX10-NEXT: v_perm_b32 v2, v2, v53, 0x5040100
+; GFX10-NEXT: v_perm_b32 v3, v20, v51, 0x5040100
+; GFX10-NEXT: v_perm_b32 v4, v12, v50, 0x5040100
+; GFX10-NEXT: v_perm_b32 v5, v5, v49, 0x5040100
+; GFX10-NEXT: v_perm_b32 v6, v6, v39, 0x5040100
+; GFX10-NEXT: v_perm_b32 v7, v7, v37, 0x5040100
+; GFX10-NEXT: v_perm_b32 v8, v8, v34, 0x5040100
+; GFX10-NEXT: v_perm_b32 v9, v9, v27, 0x5040100
+; GFX10-NEXT: v_perm_b32 v10, v10, v21, 0x5040100
+; GFX10-NEXT: v_perm_b32 v11, v69, v11, 0x5040100
+; GFX10-NEXT: v_perm_b32 v12, v68, v19, 0x5040100
+; GFX10-NEXT: v_perm_b32 v13, v67, v13, 0x5040100
+; GFX10-NEXT: v_perm_b32 v14, v66, v17, 0x5040100
+; GFX10-NEXT: v_perm_b32 v15, v16, v15, 0x5040100
; GFX10-NEXT: v_readlane_b32 s35, v31, 3
; GFX10-NEXT: v_readlane_b32 s34, v31, 2
; GFX10-NEXT: v_readlane_b32 s31, v31, 1
@@ -30035,205 +29315,198 @@ define <32 x bfloat> @v_vselect_v32bf16(<32 x i1> %cond, <32 x bfloat> %a, <32 x
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0x20
; GFX11-NEXT: scratch_load_u16 v31, off, s32
-; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:68
-; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:4
-; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:72
-; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:8
-; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:76
-; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:12
-; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:80
-; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:16
-; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:84
-; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:20
-; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:88
-; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:24
-; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:92
-; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:28
-; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:96
-; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:32
-; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:100
-; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:36
-; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:104
-; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:40
-; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:108
-; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:44
-; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:112
-; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:48
-; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:116
-; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:52
-; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:120
-; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:56
-; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:124
-; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:60
-; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:128
-; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:64
-; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
-; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
-; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; GFX11-NEXT: v_and_b32_e32 v27, 1, v27
-; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
-; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
-; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:128
+; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:64
+; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:124
+; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:60
+; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:120
+; GFX11-NEXT: scratch_load_b32 v37, off, s32 offset:56
+; GFX11-NEXT: scratch_load_b32 v38, off, s32 offset:116
+; GFX11-NEXT: scratch_load_b32 v39, off, s32 offset:52
+; GFX11-NEXT: scratch_load_b32 v48, off, s32 offset:112
+; GFX11-NEXT: scratch_load_b32 v49, off, s32 offset:48
+; GFX11-NEXT: scratch_load_b32 v50, off, s32 offset:108
+; GFX11-NEXT: scratch_load_b32 v51, off, s32 offset:44
+; GFX11-NEXT: scratch_load_b32 v52, off, s32 offset:104
+; GFX11-NEXT: scratch_load_b32 v53, off, s32 offset:40
+; GFX11-NEXT: scratch_load_b32 v54, off, s32 offset:100
+; GFX11-NEXT: scratch_load_b32 v55, off, s32 offset:36
+; GFX11-NEXT: scratch_load_b32 v64, off, s32 offset:96
+; GFX11-NEXT: scratch_load_b32 v65, off, s32 offset:32
+; GFX11-NEXT: scratch_load_b32 v66, off, s32 offset:92
+; GFX11-NEXT: scratch_load_b32 v67, off, s32 offset:28
+; GFX11-NEXT: scratch_load_b32 v68, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v69, off, s32 offset:24
+; GFX11-NEXT: scratch_load_b32 v70, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v71, off, s32 offset:20
+; GFX11-NEXT: scratch_load_b32 v80, off, s32 offset:80
+; GFX11-NEXT: scratch_load_b32 v81, off, s32 offset:16
+; GFX11-NEXT: scratch_load_b32 v82, off, s32 offset:76
+; GFX11-NEXT: scratch_load_b32 v83, off, s32 offset:12
+; GFX11-NEXT: scratch_load_b32 v84, off, s32 offset:72
+; GFX11-NEXT: scratch_load_b32 v85, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v86, off, s32 offset:68
+; GFX11-NEXT: scratch_load_b32 v87, off, s32 offset:4
+; GFX11-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX11-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX11-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX11-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX11-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30
+; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX11-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX11-NEXT: v_and_b32_e32 v16, 1, v16
; GFX11-NEXT: s_waitcnt vmcnt(30)
-; GFX11-NEXT: v_cndmask_b32_e32 v0, v32, v33, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
-; GFX11-NEXT: v_and_b32_e32 v29, 1, v29
+; GFX11-NEXT: v_cndmask_b32_e32 v30, v32, v33, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28
+; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v33
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v32
-; GFX11-NEXT: v_and_b32_e32 v30, 1, v30
+; GFX11-NEXT: v_and_b32_e32 v0, 1, v0
; GFX11-NEXT: s_waitcnt vmcnt(28)
-; GFX11-NEXT: v_cndmask_b32_e32 v2, v34, v35, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
-; GFX11-NEXT: v_and_b32_e32 v23, 1, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v28, v34, v35, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26
+; GFX11-NEXT: v_and_b32_e32 v7, 1, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v35
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v34
-; GFX11-NEXT: v_and_b32_e32 v28, 1, v28
+; GFX11-NEXT: v_and_b32_e32 v2, 1, v2
; GFX11-NEXT: s_waitcnt vmcnt(26)
-; GFX11-NEXT: v_cndmask_b32_e32 v4, v36, v37, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
-; GFX11-NEXT: v_and_b32_e32 v25, 1, v25
+; GFX11-NEXT: v_cndmask_b32_e32 v26, v36, v37, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24
+; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v37
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v36
-; GFX11-NEXT: v_and_b32_e32 v26, 1, v26
+; GFX11-NEXT: v_and_b32_e32 v4, 1, v4
; GFX11-NEXT: s_waitcnt vmcnt(24)
-; GFX11-NEXT: v_cndmask_b32_e32 v6, v38, v39, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; GFX11-NEXT: v_and_b32_e32 v19, 1, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v24, v38, v39, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22
+; GFX11-NEXT: v_and_b32_e32 v11, 1, v11
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v39
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v38
-; GFX11-NEXT: v_and_b32_e32 v24, 1, v24
+; GFX11-NEXT: v_and_b32_e32 v6, 1, v6
; GFX11-NEXT: s_waitcnt vmcnt(22)
-; GFX11-NEXT: v_cndmask_b32_e32 v8, v48, v49, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
-; GFX11-NEXT: v_and_b32_e32 v21, 1, v21
+; GFX11-NEXT: v_cndmask_b32_e32 v22, v48, v49, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20
+; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v49
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v48
-; GFX11-NEXT: v_and_b32_e32 v22, 1, v22
+; GFX11-NEXT: v_and_b32_e32 v8, 1, v8
; GFX11-NEXT: s_waitcnt vmcnt(20)
-; GFX11-NEXT: v_cndmask_b32_e32 v10, v50, v51, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX11-NEXT: v_cndmask_b32_e32 v20, v50, v51, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
; GFX11-NEXT: v_and_b32_e32 v15, 1, v15
; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v51
; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v50
-; GFX11-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX11-NEXT: v_and_b32_e32 v10, 1, v10
; GFX11-NEXT: s_waitcnt vmcnt(18)
-; GFX11-NEXT: v_cndmask_b32_e32 v12, v52, v53, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
-; GFX11-NEXT: v_and_b32_e32 v17, 1, v17
+; GFX11-NEXT: v_cndmask_b32_e32 v18, v52, v53, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v53
; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v52
-; GFX11-NEXT: v_and_b32_e32 v18, 1, v18
+; GFX11-NEXT: v_and_b32_e32 v12, 1, v12
; GFX11-NEXT: s_waitcnt vmcnt(16)
-; GFX11-NEXT: v_cndmask_b32_e32 v14, v54, v55, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v16, v54, v55, vcc_lo
; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v55
; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v54
-; GFX11-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX11-NEXT: v_and_b32_e32 v14, 1, v14
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v14
; GFX11-NEXT: s_waitcnt vmcnt(14)
-; GFX11-NEXT: v_dual_cndmask_b32 v16, v64, v65 :: v_dual_and_b32 v11, 1, v11
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v18
-; GFX11-NEXT: v_and_b32_e32 v13, 1, v13
+; GFX11-NEXT: v_dual_cndmask_b32 v14, v64, v65 :: v_dual_and_b32 v19, 1, v19
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX11-NEXT: v_and_b32_e32 v17, 1, v17
; GFX11-NEXT: v_lshrrev_b32_e32 v65, 16, v65
; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v64
; GFX11-NEXT: s_waitcnt vmcnt(12)
-; GFX11-NEXT: v_cndmask_b32_e32 v18, v66, v67, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v20
-; GFX11-NEXT: v_and_b32_e32 v7, 1, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v12, v66, v67, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v10
+; GFX11-NEXT: v_and_b32_e32 v23, 1, v23
; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v67
; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v66
; GFX11-NEXT: s_waitcnt vmcnt(10)
-; GFX11-NEXT: v_cndmask_b32_e32 v20, v68, v69, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v22
-; GFX11-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX11-NEXT: v_cndmask_b32_e32 v10, v68, v69, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX11-NEXT: v_and_b32_e32 v21, 1, v21
; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v69
; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v68
; GFX11-NEXT: s_waitcnt vmcnt(8)
-; GFX11-NEXT: v_cndmask_b32_e32 v22, v70, v71, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v24
-; GFX11-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v70, v71, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6
+; GFX11-NEXT: v_and_b32_e32 v27, 1, v27
; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v71
; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v70
; GFX11-NEXT: s_waitcnt vmcnt(6)
-; GFX11-NEXT: v_cndmask_b32_e32 v24, v80, v81, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v26
-; GFX11-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v80, v81, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4
+; GFX11-NEXT: v_and_b32_e32 v25, 1, v25
; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v81
; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v80
; GFX11-NEXT: s_waitcnt vmcnt(4)
-; GFX11-NEXT: v_cndmask_b32_e32 v26, v82, v83, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v28
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v82, v83, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v2
; GFX11-NEXT: v_and_b32_e32 v31, 1, v31
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v83
; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v82
; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: v_cndmask_b32_e32 v28, v84, v85, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v30
-; GFX11-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v84, v85, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_and_b32_e32 v29, 1, v29
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v85
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v84
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cndmask_b32_e32 v30, v86, v87, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v86, v87, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v87
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v86
-; GFX11-NEXT: v_cndmask_b32_e32 v1, v32, v33, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v31, v32, v33, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29
+; GFX11-NEXT: v_cndmask_b32_e32 v29, v34, v35, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27
+; GFX11-NEXT: v_cndmask_b32_e32 v27, v36, v37, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25
+; GFX11-NEXT: v_cndmask_b32_e32 v25, v38, v39, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23
+; GFX11-NEXT: v_cndmask_b32_e32 v23, v48, v49, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21
+; GFX11-NEXT: v_cndmask_b32_e32 v21, v50, v51, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19
+; GFX11-NEXT: v_cndmask_b32_e32 v19, v52, v53, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17
+; GFX11-NEXT: v_cndmask_b32_e32 v17, v54, v55, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
+; GFX11-NEXT: v_cndmask_b32_e32 v15, v64, v65, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
+; GFX11-NEXT: v_cndmask_b32_e32 v13, v66, v67, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
+; GFX11-NEXT: v_cndmask_b32_e32 v11, v68, v69, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v80, v81, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v3, v34, v35, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v84, v85, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v86, v87, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5
-; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v5, v36, v37, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v7, v38, v39, vcc_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v82, v83, vcc_lo
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX11-NEXT: v_perm_b32 v1, v3, v2, 0x5040100
; GFX11-NEXT: v_perm_b32 v3, v7, v6, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v9, v48, v49, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v11, v50, v51, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13
-; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v13, v52, v53, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v6, v13, v12, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v15, v54, v55, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v17
+; GFX11-NEXT: v_perm_b32 v2, v5, v4, 0x5040100
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v70, v71, vcc_lo
+; GFX11-NEXT: v_perm_b32 v5, v11, v10, 0x5040100
; GFX11-NEXT: v_perm_b32 v7, v15, v14, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v17, v64, v65, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v19
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v8, v17, v16, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v19, v66, v67, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v21
-; GFX11-NEXT: v_perm_b32 v9, v19, v18, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v21, v68, v69, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v23
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v10, v21, v20, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v23, v70, v71, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v25
; GFX11-NEXT: v_perm_b32 v11, v23, v22, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v25, v80, v81, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v27
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v4, v9, v8, 0x5040100
+; GFX11-NEXT: v_perm_b32 v8, v17, v16, 0x5040100
+; GFX11-NEXT: v_perm_b32 v9, v19, v18, 0x5040100
; GFX11-NEXT: v_perm_b32 v12, v25, v24, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v27, v82, v83, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v29
; GFX11-NEXT: v_perm_b32 v13, v27, v26, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v29, v84, v85, vcc_lo
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v31
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v14, v29, v28, 0x5040100
-; GFX11-NEXT: v_cndmask_b32_e32 v31, v86, v87, vcc_lo
; GFX11-NEXT: v_perm_b32 v15, v31, v30, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = select <32 x i1> %cond, <32 x bfloat> %a, <32 x bfloat> %b
@@ -30446,98 +29719,61 @@ define <3 x bfloat> @v_fma_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat>
; GFX8-LABEL: v_fma_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_fma_f32 v1, v1, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
-; GFX8-NEXT: v_fma_f32 v6, v8, v7, v6
+; GFX8-NEXT: v_fma_f32 v3, v6, v5, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v6, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1
-; GFX8-NEXT: v_fma_f32 v2, v6, v4, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_fma_f32 v1, v1, v3, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_fma_f32 v1, v1, v3, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_fma_f32 v6, v8, v7, v6
+; GFX9-NEXT: v_fma_f32 v3, v6, v5, v3
; GFX9-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v1
-; GFX9-NEXT: v_fma_f32 v2, v6, v4, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_fma_f32 v1, v1, v3, v4
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fma_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_fmac_f32_e32 v6, v8, v7
; GFX10-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX10-NEXT: v_fmac_f32_e32 v9, v11, v10
; GFX10-NEXT: v_fmac_f32_e32 v5, v1, v3
; GFX10-NEXT: v_perm_b32 v0, v4, v6, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v5, v9, 0x7060302
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v5, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fma_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v9, v11, v10 :: v_dual_fmac_f32 v6, v8, v7
-; GFX11-NEXT: v_perm_b32 v1, v5, v9, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v4, v6, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <3 x bfloat> @llvm.fma.v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat> %c)
ret <3 x bfloat> %op
}
@@ -30596,97 +29832,97 @@ define <4 x bfloat> @v_fma_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat>
; GFX8-LABEL: v_fma_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
-; GFX8-NEXT: v_fma_f32 v6, v8, v7, v6
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v6, 16
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v1
-; GFX8-NEXT: v_fma_f32 v2, v6, v4, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_fma_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, v8, v7, v6
+; GFX8-NEXT: v_fma_f32 v1, v1, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_fma_f32 v3, v7, v5, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_fma_f32 v6, v8, v7, v6
+; GFX9-NEXT: v_fma_f32 v1, v1, v3, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_fma_f32 v6, v8, v7, v6
+; GFX9-NEXT: v_fma_f32 v3, v7, v5, v3
; GFX9-NEXT: v_fma_f32 v0, v0, v2, v4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v5
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v1
-; GFX9-NEXT: v_fma_f32 v2, v6, v4, v2
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v5
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_fma_f32 v1, v1, v3, v4
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fma_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_fmac_f32_e32 v6, v8, v7
-; GFX10-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX10-NEXT: v_fmac_f32_e32 v9, v11, v10
+; GFX10-NEXT: v_fmac_f32_e32 v4, v0, v2
; GFX10-NEXT: v_fmac_f32_e32 v5, v1, v3
-; GFX10-NEXT: v_perm_b32 v0, v4, v6, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v5, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v4, v9, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v5, v6, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fma_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_fmac_f32 v9, v11, v10 :: v_dual_lshlrev_b32 v6, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-NEXT: v_dual_fmac_f32 v4, v0, v2 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v5, v1, v3 :: v_dual_and_b32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_fmac_f32_e32 v4, v0, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v9, v11, v10 :: v_dual_fmac_f32 v6, v8, v7
-; GFX11-NEXT: v_perm_b32 v1, v5, v9, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v4, v6, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v4, v9, 0x7060302
+; GFX11-NEXT: v_fmac_f32_e32 v5, v1, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fmac_f32_e32 v6, v8, v7
+; GFX11-NEXT: v_perm_b32 v1, v5, v6, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.fma.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat> %c)
ret <4 x bfloat> %op
@@ -30948,133 +30184,79 @@ define <3 x bfloat> @v_fmuladd_v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfl
; GFX8-LABEL: v_fmuladd_v3bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v5
+; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; GFX8-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v6, 16
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmuladd_v3bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v5
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_mul_f32_e32 v3, v5, v3
; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; GFX9-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v5
; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, v4, v2
-; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; GFX9-NEXT: v_add_f32_e32 v6, v6, v7
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmuladd_v3bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
-; GFX10-NEXT: v_mul_f32_e32 v6, v8, v7
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v5
+; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX10-NEXT: v_mul_f32_e32 v3, v7, v6
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v7
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX10-NEXT: v_add_f32_e32 v3, v4, v6
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX10-NEXT: v_add_f32_e32 v1, v1, v5
+; GFX10-NEXT: v_add_f32_e32 v2, v2, v3
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v1, 16
; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-LABEL: v_fmuladd_v3bf16:
-; GFX11: ; %bb.0:
-; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_dual_mul_f32 v6, v7, v6 :: v_dual_lshlrev_b32 v7, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mul_f32_e32 v6, v8, v7
-; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v7 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_add_f32_e32 v3, v4, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
-; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <3 x bfloat> @llvm.fmuladd.v3bf16(<3 x bfloat> %a, <3 x bfloat> %b, <3 x bfloat> %c)
ret <3 x bfloat> %op
}
@@ -31149,132 +30331,131 @@ define <4 x bfloat> @v_fmuladd_v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfl
; GFX8-LABEL: v_fmuladd_v4bf16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; GFX8-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX8-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX8-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
-; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v7, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v7, 16, v5
; GFX8-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, v5, v3
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
; GFX8-NEXT: v_add_f32_e32 v6, v6, v7
-; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX8-NEXT: v_add_f32_e32 v2, v2, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_alignbit_b32 v0, v0, v6, 16
-; GFX8-NEXT: v_alignbit_b32 v1, v1, v2, 16
+; GFX8-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX8-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX8-NEXT: v_alignbit_b32 v0, v0, v3, 16
+; GFX8-NEXT: v_alignbit_b32 v1, v1, v6, 16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fmuladd_v4bf16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
-; GFX9-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_mul_f32_e32 v2, v4, v2
; GFX9-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v5
+; GFX9-NEXT: v_mul_f32_e32 v6, v7, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_mul_f32_e32 v3, v5, v3
+; GFX9-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX9-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v4
; GFX9-NEXT: v_add_f32_e32 v6, v6, v7
+; GFX9-NEXT: v_add_f32_e32 v3, v3, v5
+; GFX9-NEXT: v_add_f32_e32 v0, v0, v2
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
-; GFX9-NEXT: v_add_f32_e32 v2, v2, v4
-; GFX9-NEXT: v_add_f32_e32 v1, v1, v3
-; GFX9-NEXT: v_perm_b32 v0, v0, v6, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v3, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_fmuladd_v4bf16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v8, 16, v0
+; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX10-NEXT: v_mul_f32_e32 v6, v7, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
-; GFX10-NEXT: v_mul_f32_e32 v6, v8, v7
+; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX10-NEXT: v_mul_f32_e32 v3, v8, v7
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
-; GFX10-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
-; GFX10-NEXT: v_add_f32_e32 v2, v2, v7
-; GFX10-NEXT: v_add_f32_e32 v0, v0, v3
-; GFX10-NEXT: v_add_f32_e32 v3, v4, v6
+; GFX10-NEXT: v_add_f32_e32 v2, v6, v2
+; GFX10-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v4
; GFX10-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
+; GFX10-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fmuladd_v4bf16:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v0
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_dual_mul_f32 v6, v7, v6 :: v_dual_and_b32 v3, 0xffff0000, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v2
+; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_and_b32_e32 v6, 0xffff0000, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_mul_f32_e32 v0, v0, v2
-; GFX11-NEXT: v_dual_mul_f32 v6, v7, v6 :: v_dual_lshlrev_b32 v7, 16, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: v_and_b32_e32 v2, 0xffff0000, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mul_f32_e32 v6, v8, v7
-; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
-; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_dual_add_f32 v2, v6, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX11-NEXT: v_mul_f32_e32 v3, v8, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_and_b32 v1, 0xffff0000, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_dual_add_f32 v2, v2, v7 :: v_dual_and_b32 v5, 0xffff0000, v5
-; GFX11-NEXT: v_add_f32_e32 v3, v4, v6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_add_f32 v0, v0, v4 :: v_dual_and_b32 v3, 0xffff0000, v3
; GFX11-NEXT: v_add_f32_e32 v1, v1, v5
-; GFX11-NEXT: v_perm_b32 v0, v0, v2, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX11-NEXT: v_perm_b32 v1, v1, v2, 0x7060302
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v1, v1, v3, 0x7060302
+; GFX11-NEXT: v_perm_b32 v0, v0, v3, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%op = call <4 x bfloat> @llvm.fmuladd.v4bf16(<4 x bfloat> %a, <4 x bfloat> %b, <4 x bfloat> %c)
ret <4 x bfloat> %op
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index ef2be37d62d9df..160bae51193ea0 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -3165,11 +3165,11 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dwordx4 v[16:19], off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:8
-; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:12
-; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:20
-; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:16
-; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
+; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4
+; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:8
+; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:20
+; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:16
+; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0
@@ -3178,16 +3178,14 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: buffer_store_dword v20, off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: buffer_store_dword v16, off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: buffer_store_dword v17, off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v18, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v19, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dword v20, off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_store_dwordx2 v[16:17], off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16:
@@ -3205,11 +3203,11 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dwordx4 v[16:19], off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:8
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:12
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:4
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:8
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -3219,16 +3217,14 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v20, off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v16, off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v17, off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v18, off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v19, off, s[4:7], 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v20, off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dwordx2 v[16:17], off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16:
@@ -3236,11 +3232,11 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:4
-; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:8
-; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:12
-; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:20
-; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:16
+; GFX11-NEXT: scratch_load_b32 v33, off, s32 offset:20
+; GFX11-NEXT: scratch_load_b32 v34, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v35, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v36, off, s32 offset:12
+; GFX11-NEXT: scratch_load_b32 v32, off, s32 offset:16
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
; GFX11-NEXT: s_waitcnt vmcnt(5)
@@ -3260,20 +3256,17 @@ define void @void_func_v32i32_v2i16_v2f16_v2bf16_v4bf16(<32 x i32> %arg0, <2 x i
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[0:3], 0 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX11-NEXT: s_waitcnt vmcnt(4)
-; GFX11-NEXT: buffer_store_b32 v32, off, s[0:3], 0 dlc
-; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_waitcnt vmcnt(3)
-; GFX11-NEXT: buffer_store_b32 v33, off, s[0:3], 0 dlc
+; GFX11-NEXT: buffer_store_b32 v34, off, s[0:3], 0 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: buffer_store_b32 v34, off, s[0:3], 0 dlc
+; GFX11-NEXT: buffer_store_b32 v35, off, s[0:3], 0 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: buffer_store_b32 v35, off, s[0:3], 0 dlc
+; GFX11-NEXT: buffer_store_b32 v36, off, s[0:3], 0 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: buffer_store_b32 v36, off, s[0:3], 0 dlc
+; GFX11-NEXT: buffer_store_b64 v[32:33], off, s[0:3], 0 dlc
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-NEXT: s_setpc_b64 s[30:31]
store volatile <32 x i32> %arg0, ptr addrspace(1) undef
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
index ca3336beccf773..8dcd0f504e5091 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
@@ -948,57 +948,52 @@ define <3 x i1> @isnan_v3bf16(<3 x bfloat> %x) nounwind {
; GFX8CHECK-LABEL: isnan_v3bf16:
; GFX8CHECK: ; %bb.0:
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX8CHECK-NEXT: v_and_b32_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8CHECK-NEXT: v_and_b32_e32 v2, 0x7fff, v1
; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX8CHECK-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX8CHECK-NEXT: v_bfe_u32 v1, v0, 16, 15
+; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
-; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v2
+; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX9CHECK-LABEL: isnan_v3bf16:
; GFX9CHECK: ; %bb.0:
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9CHECK-NEXT: v_and_b32_sdwa v3, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX9CHECK-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v0
; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX9CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
; GFX9CHECK-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
+; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
+; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s4 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
-; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX10CHECK-LABEL: isnan_v3bf16:
; GFX10CHECK: ; %bb.0:
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX10CHECK-NEXT: v_and_b32_e32 v3, 0x7fff, v0
+; GFX10CHECK-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v0
+; GFX10CHECK-NEXT: v_mov_b32_e32 v3, 0x7f80
; GFX10CHECK-NEXT: v_and_b32_e32 v4, 0x7fff, v1
-; GFX10CHECK-NEXT: v_and_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3
-; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2
-; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v2, v3 src0_sel:WORD_1 src1_sel:DWORD
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11CHECK-LABEL: isnan_v3bf16:
; GFX11CHECK: ; %bb.0:
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX11CHECK-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX11CHECK-NEXT: v_and_b32_e32 v3, 0x7fff, v1
-; GFX11CHECK-NEXT: v_and_b32_e32 v2, 0x7fff, v2
+; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v2
@@ -1032,18 +1027,17 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX8CHECK-LABEL: isnan_v4bf16:
; GFX8CHECK: ; %bb.0:
; GFX8CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8CHECK-NEXT: v_mov_b32_e32 v2, 0x7fff
+; GFX8CHECK-NEXT: v_bfe_u32 v3, v1, 16, 15
; GFX8CHECK-NEXT: s_movk_i32 s4, 0x7f80
-; GFX8CHECK-NEXT: v_and_b32_sdwa v4, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX8CHECK-NEXT: v_and_b32_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8CHECK-NEXT: v_and_b32_e32 v1, 0x7fff, v1
+; GFX8CHECK-NEXT: v_and_b32_e32 v2, 0x7fff7fff, v1
+; GFX8CHECK-NEXT: v_bfe_u32 v1, v0, 16, 15
+; GFX8CHECK-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v0
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v1
-; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v4
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v2
+; GFX8CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s4, v3
; GFX8CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX8CHECK-NEXT: s_setpc_b64 s[30:31]
@@ -1051,56 +1045,49 @@ define <4 x i1> @isnan_v4bf16(<4 x bfloat> %x) nounwind {
; GFX9CHECK-LABEL: isnan_v4bf16:
; GFX9CHECK: ; %bb.0:
; GFX9CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9CHECK-NEXT: s_movk_i32 s4, 0x7fff
-; GFX9CHECK-NEXT: s_movk_i32 s5, 0x7f80
-; GFX9CHECK-NEXT: v_and_b32_sdwa v4, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX9CHECK-NEXT: v_and_b32_sdwa v3, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX9CHECK-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s5, v0
+; GFX9CHECK-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v1
+; GFX9CHECK-NEXT: s_movk_i32 s6, 0x7f80
+; GFX9CHECK-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v0
+; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s6, v1
+; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v1, s6 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s5, v1
+; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s6, v3
+; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
+; GFX9CHECK-NEXT: v_cmp_gt_i16_sdwa s[4:5], v3, s6 src0_sel:WORD_1 src1_sel:DWORD
; GFX9CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s5, v4
-; GFX9CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX9CHECK-NEXT: v_cmp_lt_i16_e32 vcc, s5, v3
-; GFX9CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
+; GFX9CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5]
; GFX9CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX10CHECK-LABEL: isnan_v4bf16:
; GFX10CHECK: ; %bb.0:
; GFX10CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10CHECK-NEXT: v_and_b32_e32 v3, 0x7fff, v0
-; GFX10CHECK-NEXT: v_mov_b32_e32 v2, 0x7fff
-; GFX10CHECK-NEXT: v_and_b32_e32 v4, 0x7fff, v1
+; GFX10CHECK-NEXT: v_and_b32_e32 v3, 0x7fff7fff, v0
+; GFX10CHECK-NEXT: v_mov_b32_e32 v5, 0x7f80
+; GFX10CHECK-NEXT: v_and_b32_e32 v4, 0x7fff7fff, v1
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3
-; GFX10CHECK-NEXT: v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10CHECK-NEXT: v_and_b32_sdwa v1, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v3, v5 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10CHECK-NEXT: v_cmp_gt_i16_sdwa s4, v4, v5 src0_sel:WORD_1 src1_sel:DWORD
; GFX10CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1
-; GFX10CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v5
-; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; GFX10CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, s4
; GFX10CHECK-NEXT: s_setpc_b64 s[30:31]
;
; GFX11CHECK-LABEL: isnan_v4bf16:
; GFX11CHECK: ; %bb.0:
; GFX11CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11CHECK-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11CHECK-NEXT: v_and_b32_e32 v1, 0x7fff, v1
-; GFX11CHECK-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; GFX11CHECK-NEXT: v_and_b32_e32 v0, 0x7fff7fff, v0
+; GFX11CHECK-NEXT: v_and_b32_e32 v1, 0x7fff7fff, v1
; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v0
-; GFX11CHECK-NEXT: v_and_b32_e32 v4, 0x7fff, v2
+; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11CHECK-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v1
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3
-; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v4
+; GFX11CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; GFX11CHECK-NEXT: v_cmp_lt_i16_e32 vcc_lo, 0x7f80, v3
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
%1 = call <4 x i1> @llvm.is.fpclass.v4bf16(<4 x bfloat> %x, i32 3) ; nan
diff --git a/llvm/test/CodeGen/AMDGPU/select-undef.ll b/llvm/test/CodeGen/AMDGPU/select-undef.ll
index 8ca33dce73f880..5b9866a3c91571 100644
--- a/llvm/test/CodeGen/AMDGPU/select-undef.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-undef.ll
@@ -303,9 +303,8 @@ ret:
ret void
}
-; FIXME: This shouldn't have the 0 initialization
; GCN-LABEL: {{^}}undef_v3bf16:
-; GCN: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
+; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0{{$}}
; GCN: s_cbranch_vccnz
define amdgpu_kernel void @undef_v3bf16(ptr addrspace(3) %ptr, i1 %cond) {
diff --git a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
index dfe98bbbaddf9e..d76bb48b4a82a3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll
@@ -2703,30 +2703,30 @@ define <4 x bfloat> @shuffle_v4bf16_234u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_234u:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[0:1], off offset:4
-; GFX9-NEXT: global_load_dword v5, v[2:3], off
+; GFX9-NEXT: global_load_dword v6, v[0:1], off offset:4
+; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_mov_b32_e32 v0, v6
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_234u:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[0:1], off offset:4
-; GFX10-NEXT: global_load_dword v5, v[2:3], off
+; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:4
+; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_mov_b32_e32 v0, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v1, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_234u:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b32 v1, v[2:3], off
+; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -2935,32 +2935,35 @@ define <4 x bfloat> @shuffle_v4bf16_357u(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_357u:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v6, v[0:1], off offset:4
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX9-NEXT: global_load_dword v6, v[0:1], off offset:4
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_alignbit_b32 v1, s4, v5, 16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v4, v6, s4
-; GFX9-NEXT: v_alignbit_b32 v1, s4, v5, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_357u:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:4
; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_alignbit_b32 v1, s4, v5, 16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, v4, v6, 0x7060302
-; GFX10-NEXT: v_alignbit_b32 v1, s4, v5, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_357u:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v4, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b64 v[0:1], v[2:3], off
+; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
+; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_alignbit_b32 v1, s0, v3, 16
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_perm_b32 v0, v0, v4, 0x7060302
-; GFX11-NEXT: v_alignbit_b32 v1, s0, v1, 16
+; GFX11-NEXT: v_perm_b32 v0, v2, v0, 0x7060302
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
@@ -2972,24 +2975,29 @@ define <4 x bfloat> @shuffle_v4bf16_0101(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_0101:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_0101:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_0101:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3029,31 +3037,39 @@ define <4 x bfloat> @shuffle_v4bf16_0145(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_0145:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[0:1], off
-; GFX9-NEXT: global_load_dword v5, v[2:3], off
+; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
+; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v4, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_bfi_b32 v1, s4, v5, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_0145:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[0:1], off
-; GFX10-NEXT: global_load_dword v5, v[2:3], off
+; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX10-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX10-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v4, v4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v5, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_0145:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
-; GFX11-NEXT: global_load_b32 v1, v[2:3], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
+; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
@@ -3065,30 +3081,33 @@ define <4 x bfloat> @shuffle_v4bf16_0167(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_0167:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[0:1], off
-; GFX9-NEXT: global_load_dword v5, v[2:3], off offset:4
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
+; GFX9-NEXT: global_load_dword v4, v[2:3], off offset:4
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v5, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_0167:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[0:1], off
-; GFX10-NEXT: global_load_dword v5, v[2:3], off offset:4
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
+; GFX10-NEXT: global_load_dword v4, v[2:3], off offset:4
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v5, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v1, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_0167:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: global_load_b32 v1, v[2:3], off offset:4
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3102,7 +3121,9 @@ define <4 x bfloat> @shuffle_v4bf16_2301(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[1:2], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v1
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3111,6 +3132,7 @@ define <4 x bfloat> @shuffle_v4bf16_2301(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[1:2], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3119,6 +3141,7 @@ define <4 x bfloat> @shuffle_v4bf16_2301(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b64 v[1:2], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3161,30 +3184,33 @@ define <4 x bfloat> @shuffle_v4bf16_2345(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_2345:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
; GFX9-NEXT: global_load_dword v4, v[0:1], off offset:4
-; GFX9-NEXT: global_load_dword v5, v[2:3], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v1, s4, v5, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_2345:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
; GFX10-NEXT: global_load_dword v4, v[0:1], off offset:4
-; GFX10-NEXT: global_load_dword v5, v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v5, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_2345:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b32 v1, v[2:3], off
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v2, v2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3233,33 +3259,39 @@ define <4 x bfloat> @shuffle_v4bf16_4501(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_4501:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[2:3], off
-; GFX9-NEXT: global_load_dword v5, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
+; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v4, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_bfi_b32 v1, s4, v5, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_4501:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[2:3], off
-; GFX10-NEXT: global_load_dword v5, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
+; GFX10-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX10-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v4, v4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v5, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_4501:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v2, v[2:3], off
-; GFX11-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
+; GFX11-NEXT: global_load_b64 v[3:4], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v2, v2
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v3, v3
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
@@ -3271,32 +3303,33 @@ define <4 x bfloat> @shuffle_v4bf16_4523(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_4523:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[2:3], off
-; GFX9-NEXT: global_load_dword v5, v[0:1], off offset:4
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX9-NEXT: global_load_dword v4, v[0:1], off offset:4
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v5, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v1, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_4523:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[2:3], off
-; GFX10-NEXT: global_load_dword v5, v[0:1], off offset:4
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX10-NEXT: global_load_dword v4, v[0:1], off offset:4
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v5, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v1, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_4523:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v2, v[2:3], off
+; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-NEXT: global_load_b32 v1, v[0:1], off offset:4
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v2, v2
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3309,24 +3342,29 @@ define <4 x bfloat> @shuffle_v4bf16_4545(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_4545:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v0, v[2:3], off
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[2:3], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_4545:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v[2:3], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_4545:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[2:3], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3366,32 +3404,33 @@ define <4 x bfloat> @shuffle_v4bf16_6701(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_6701:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
; GFX9-NEXT: global_load_dword v4, v[2:3], off offset:4
-; GFX9-NEXT: global_load_dword v5, v[0:1], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v1, s4, v5, v5
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_mov_b32_e32 v0, v4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_6701:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[0:1], off
; GFX10-NEXT: global_load_dword v4, v[2:3], off offset:4
-; GFX10-NEXT: global_load_dword v5, v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v5, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_mov_b32_e32 v0, v4
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_6701:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v2, v[2:3], off offset:4
-; GFX11-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[4:5], v[0:1], off
+; GFX11-NEXT: global_load_b32 v0, v[2:3], off offset:4
; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v4, v4
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3443,7 +3482,9 @@ define <4 x bfloat> @shuffle_v4bf16_6745(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[1:2], v[2:3], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_bfi_b32 v1, s4, v1, v1
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
@@ -3452,6 +3493,7 @@ define <4 x bfloat> @shuffle_v4bf16_6745(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[1:2], v[2:3], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX10-NEXT: v_mov_b32_e32 v0, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -3460,6 +3502,7 @@ define <4 x bfloat> @shuffle_v4bf16_6745(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX11-NEXT: v_mov_b32_e32 v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
@@ -3578,31 +3621,34 @@ define <4 x bfloat> @shuffle_v4bf16_3456(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_3456:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v6, v[0:1], off offset:4
; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX9-NEXT: global_load_dword v6, v[0:1], off offset:4
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_alignbit_b32 v1, v5, v4, 16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_alignbit_b32 v0, v4, v6, 16
-; GFX9-NEXT: v_alignbit_b32 v1, v5, v4, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_3456:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:4
; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX10-NEXT: global_load_dword v6, v[0:1], off offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_alignbit_b32 v1, v5, v4, 16
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v0, v4, v6, 16
-; GFX10-NEXT: v_alignbit_b32 v1, v5, v4, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_3456:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: global_load_b64 v[2:3], v[2:3], off
; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:4
-; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_alignbit_b32 v1, v3, v2, 16
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_alignbit_b32 v0, v1, v0, 16
-; GFX11-NEXT: v_alignbit_b32 v1, v2, v1, 16
+; GFX11-NEXT: v_alignbit_b32 v0, v2, v0, 16
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <4 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <4 x bfloat>, ptr addrspace(1) %arg1
@@ -3693,7 +3739,7 @@ define <4 x bfloat> @shuffle_v4bf16_0000(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_0000:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v0, s4
@@ -3703,7 +3749,7 @@ define <4 x bfloat> @shuffle_v4bf16_0000(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-LABEL: shuffle_v4bf16_0000:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, v0, v0, 0x5040100
; GFX10-NEXT: v_mov_b32_e32 v1, v0
@@ -3712,7 +3758,7 @@ define <4 x bfloat> @shuffle_v4bf16_0000(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-LABEL: shuffle_v4bf16_0000:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_perm_b32 v0, v0, v0, 0x5040100
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3728,7 +3774,7 @@ define <4 x bfloat> @shuffle_v4bf16_1010(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_1010:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_alignbit_b32 v0, v0, v0, 16
; GFX9-NEXT: v_mov_b32_e32 v1, v0
@@ -3737,7 +3783,7 @@ define <4 x bfloat> @shuffle_v4bf16_1010(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-LABEL: shuffle_v4bf16_1010:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v0, v0, v0, 16
; GFX10-NEXT: v_mov_b32_e32 v1, v0
@@ -3746,7 +3792,7 @@ define <4 x bfloat> @shuffle_v4bf16_1010(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-LABEL: shuffle_v4bf16_1010:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v0, v0, v0, 16
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
@@ -3762,7 +3808,7 @@ define <4 x bfloat> @shuffle_v4bf16_1100(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_1100:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v1, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[1:2], v[0:1], off
; GFX9-NEXT: s_mov_b32 s4, 0x7060302
; GFX9-NEXT: s_mov_b32 s5, 0x5040100
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -3773,7 +3819,7 @@ define <4 x bfloat> @shuffle_v4bf16_1100(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-LABEL: shuffle_v4bf16_1100:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v1, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[1:2], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, v1, v1, 0x7060302
; GFX10-NEXT: v_perm_b32 v1, v1, v1, 0x5040100
@@ -3782,7 +3828,7 @@ define <4 x bfloat> @shuffle_v4bf16_1100(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-LABEL: shuffle_v4bf16_1100:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v1, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[1:2], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_perm_b32 v0, v1, v1, 0x7060302
; GFX11-NEXT: v_perm_b32 v1, v1, v1, 0x5040100
@@ -3897,24 +3943,29 @@ define <4 x bfloat> @shuffle_v8bf16_0101(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v8bf16_0101:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v0, v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
; GFX9-NEXT: v_mov_b32_e32 v1, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v8bf16_0101:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v0, v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX10-NEXT: v_mov_b32_e32 v1, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v8bf16_0101:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v1, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <8 x bfloat>, ptr addrspace(1) %arg0
@@ -3954,31 +4005,39 @@ define <4 x bfloat> @shuffle_v8bf16_4589(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v8bf16_4589:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v4, v[0:1], off offset:8
-; GFX9-NEXT: global_load_dword v5, v[2:3], off
+; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:8
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
+; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_mov_b32_e32 v0, v4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v4, v4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_mov_b32_e32 v1, v5
+; GFX9-NEXT: v_bfi_b32 v1, s4, v5, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v8bf16_4589:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v4, v[0:1], off offset:8
-; GFX10-NEXT: global_load_dword v5, v[2:3], off
+; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off offset:8
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX10-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX10-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v4, v4
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_mov_b32_e32 v1, v5
+; GFX10-NEXT: v_bfi_b32 v1, 0xffff, v5, v5
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v8bf16_4589:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off offset:8
-; GFX11-NEXT: global_load_b32 v1, v[2:3], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off offset:8
+; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
+; GFX11-NEXT: s_waitcnt vmcnt(1)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v1, 0xffff, v1, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <8 x bfloat>, ptr addrspace(1) %arg0
%val1 = load <8 x bfloat>, ptr addrspace(1) %arg1
@@ -4067,9 +4126,11 @@ define <4 x bfloat> @shuffle_v3bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
-; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: s_mov_b32 s4, 0xffff
+; GFX9-NEXT: s_mov_b32 s5, 0x5040100
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v1, v1, s4
+; GFX9-NEXT: v_bfi_b32 v0, s4, v0, v0
+; GFX9-NEXT: v_perm_b32 v1, v1, v1, s5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v3bf16_0122:
@@ -4077,6 +4138,7 @@ define <4 x bfloat> @shuffle_v3bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX10-NEXT: v_perm_b32 v1, v1, v1, 0x5040100
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
@@ -4085,6 +4147,7 @@ define <4 x bfloat> @shuffle_v3bf16_0122(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: v_bfi_b32 v0, 0xffff, v0, v0
; GFX11-NEXT: v_perm_b32 v1, v1, v1, 0x5040100
; GFX11-NEXT: s_setpc_b64 s[30:31]
%val0 = load <3 x bfloat>, ptr addrspace(1) %arg0
@@ -4190,27 +4253,27 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff0000, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_fma_f32 v7, v8, v9, v7
; GFX9-NEXT: v_fma_f32 v0, v8, v4, v0
-; GFX9-NEXT: v_fma_f32 v4, v11, v4, v12
-; GFX9-NEXT: v_fma_f32 v1, v11, v9, v1
+; GFX9-NEXT: v_fma_f32 v8, v12, v9, v11
+; GFX9-NEXT: v_fma_f32 v1, v12, v4, v1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff0000, v4
+; GFX9-NEXT: v_and_b32_e32 v7, 0xffff0000, v8
; GFX9-NEXT: v_fma_f32 v0, v2, v10, v0
-; GFX9-NEXT: v_fma_f32 v2, v2, v5, v7
-; GFX9-NEXT: v_fma_f32 v1, v3, v5, v1
-; GFX9-NEXT: v_fma_f32 v3, v3, v10, v4
+; GFX9-NEXT: v_fma_f32 v2, v2, v5, v4
+; GFX9-NEXT: v_fma_f32 v1, v3, v10, v1
+; GFX9-NEXT: v_fma_f32 v3, v3, v5, v7
+; GFX9-NEXT: v_perm_b32 v1, v3, v1, s0
; GFX9-NEXT: v_perm_b32 v0, v2, v0, s0
-; GFX9-NEXT: v_perm_b32 v1, v1, v3, s0
; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
;
@@ -4233,27 +4296,27 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX10-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v3
-; GFX10-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX10-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX10-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX10-NEXT: v_fmac_f32_e32 v7, v8, v9
; GFX10-NEXT: v_fmac_f32_e32 v0, v8, v4
; GFX10-NEXT: v_and_b32_e32 v2, 0xffff0000, v2
-; GFX10-NEXT: v_fmac_f32_e32 v12, v11, v9
-; GFX10-NEXT: v_fmac_f32_e32 v1, v11, v4
-; GFX10-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX10-NEXT: v_fmac_f32_e32 v11, v10, v4
+; GFX10-NEXT: v_fmac_f32_e32 v1, v10, v9
+; GFX10-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
; GFX10-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
-; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v12
+; GFX10-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
; GFX10-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
-; GFX10-NEXT: v_fmac_f32_e32 v0, v2, v10
-; GFX10-NEXT: v_fmac_f32_e32 v4, v2, v5
-; GFX10-NEXT: v_fmac_f32_e32 v7, v3, v5
-; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v10
-; GFX10-NEXT: v_perm_b32 v0, v4, v0, 0x7060302
-; GFX10-NEXT: v_perm_b32 v1, v7, v1, 0x7060302
+; GFX10-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX10-NEXT: v_fmac_f32_e32 v0, v2, v12
+; GFX10-NEXT: v_fmac_f32_e32 v4, v3, v12
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v5
+; GFX10-NEXT: v_fmac_f32_e32 v7, v2, v5
+; GFX10-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX10-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
; GFX10-NEXT: global_store_dwordx2 v6, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
;
@@ -4269,36 +4332,36 @@ define amdgpu_kernel void @fma_shuffle_v2bf16(ptr addrspace(1) nocapture readonl
; GFX11-NEXT: global_load_b64 v[2:3], v6, s[0:1]
; GFX11-NEXT: global_load_b64 v[4:5], v6, s[2:3]
; GFX11-NEXT: s_waitcnt vmcnt(2)
-; GFX11-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-NEXT: s_waitcnt vmcnt(1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; GFX11-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff0000, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v3
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff0000, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v2
-; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v1, v11, v4 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_fmac_f32_e32 v1, v10, v9
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v1, v3, v10 :: v_dual_fmac_f32 v0, v8, v4
+; GFX11-NEXT: v_dual_fmac_f32 v1, v3, v5 :: v_dual_lshlrev_b32 v4, 16, v4
+; GFX11-NEXT: v_dual_fmac_f32 v11, v10, v4 :: v_dual_lshlrev_b32 v8, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_dual_fmac_f32 v7, v8, v9 :: v_dual_and_b32 v2, 0xffff0000, v2
+; GFX11-NEXT: v_fmac_f32_e32 v0, v8, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v11
+; GFX11-NEXT: v_and_b32_e32 v7, 0xffff0000, v7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_fmac_f32_e32 v0, v2, v10
-; GFX11-NEXT: v_fmac_f32_e32 v12, v11, v9
-; GFX11-NEXT: v_fmac_f32_e32 v7, v8, v9
-; GFX11-NEXT: v_and_b32_e32 v4, 0xffff0000, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_dual_fmac_f32 v4, v2, v5 :: v_dual_and_b32 v7, 0xffff0000, v12
-; GFX11-NEXT: v_fmac_f32_e32 v7, v3, v5
+; GFX11-NEXT: v_dual_fmac_f32 v4, v3, v12 :: v_dual_fmac_f32 v7, v2, v5
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v0, v4, v0, 0x7060302
-; GFX11-NEXT: v_perm_b32 v1, v7, v1, 0x7060302
+; GFX11-NEXT: v_fmac_f32_e32 v0, v2, v12
+; GFX11-NEXT: v_perm_b32 v1, v1, v4, 0x7060302
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v0, v7, v0, 0x7060302
; GFX11-NEXT: global_store_b64 v6, v[0:1], s[4:5]
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -4336,28 +4399,32 @@ define <4 x bfloat> @shuffle_v4bf16_0456(ptr addrspace(1) %arg0, ptr addrspace(1
; GFX9-LABEL: shuffle_v4bf16_0456:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: global_load_dword v6, v[0:1], off
-; GFX9-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX9-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
+; GFX9-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
; GFX9-NEXT: s_mov_b32 s4, 0x5040100
+; GFX9-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX9-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v0, v4, v6, s4
-; GFX9-NEXT: v_alignbit_b32 v1, v5, v4, 16
+; GFX9-NEXT: v_perm_b32 v0, v5, v4, s4
+; GFX9-NEXT: v_alignbit_b32 v1, v6, v5, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: shuffle_v4bf16_0456:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: global_load_dword v6, v[0:1], off
-; GFX10-NEXT: global_load_dwordx2 v[4:5], v[2:3], off
+; GFX10-NEXT: global_load_dwordx2 v[4:5], v[0:1], off
+; GFX10-NEXT: global_load_dwordx2 v[5:6], v[2:3], off
+; GFX10-NEXT: ; kill: killed $vgpr0 killed $vgpr1
+; GFX10-NEXT: ; kill: killed $vgpr2 killed $vgpr3
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, v4, v6, 0x5040100
-; GFX10-NEXT: v_alignbit_b32 v1, v5, v4, 16
+; GFX10-NEXT: v_perm_b32 v0, v5, v4, 0x5040100
+; GFX10-NEXT: v_alignbit_b32 v1, v6, v5, 16
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: shuffle_v4bf16_0456:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: global_load_b32 v0, v[0:1], off
+; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off
; GFX11-NEXT: global_load_b64 v[1:2], v[2:3], off
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: v_perm_b32 v0, v1, v0, 0x5040100
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