[llvm] [RISCV] Don't call use_nodbg_operands for physical registers in RISCVOptWInstrs hasAllNBitUsers. (PR #77032)

[Craig Topper via llvm-commits]

https://github.com/topperc created https://github.com/llvm/llvm-project/pull/77032

The ADDIW in the new test case was incorrectly removed due to incorrectly following the x10 register from the return value back to the argument. This is due to use_nodbg_operands returning every instruction that uses a physical register regardless of the data flow.

>From cd9f4e02baad15cfa557a1b8dfe2ba0eb043ce37 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 4 Jan 2024 17:19:03 -0800
Subject: [PATCH] [RISCV] Don't call use_nodbg_operands for physical registers
 in RISCVOptWInstrs hasAllNBitUsers.

The ADDIW in the new test case was incorrectly removed due to
incorrectly following the x10 register from the return value back
to the argument.
---
 llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp |  3 +++
 llvm/test/CodeGen/RISCV/opt-w-instrs.mir  | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
index 2c2b34bb5b7797..b9dde29d05a369 100644
--- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
+++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
@@ -126,6 +126,9 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
     if (MI->getNumExplicitDefs() != 1)
       return false;
 
+    if (!MI->getOperand(0).getReg().isVirtual())
+      return false;
+
     for (auto &UserOp : MRI.use_nodbg_operands(MI->getOperand(0).getReg())) {
       const MachineInstr *UserMI = UserOp.getParent();
       unsigned OpIdx = UserOp.getOperandNo();
diff --git a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
index 0ecf8fd6bef33a..ebac5a42fbcda0 100644
--- a/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
+++ b/llvm/test/CodeGen/RISCV/opt-w-instrs.mir
@@ -28,3 +28,23 @@ body:             |
     $x11 = COPY %4
     PseudoRET
 ...
+
+---
+name:            physreg
+tracksRegLiveness: true
+body:             |
+  bb.0.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-ZFA-LABEL: name: physreg
+    ; CHECK-ZFA: liveins: $x10, $x11
+    ; CHECK-ZFA-NEXT: {{  $}}
+    ; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
+    ; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
+    ; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]]
+    ; CHECK-ZFA-NEXT: PseudoRET
+    %0:gpr = COPY $x10
+    %1:gpr = ADDIW %0, 0
+    $x10 = COPY %1
+    PseudoRET
+...