[llvm] [InstCombine] Extend ADD+GEP->GEP+GEP combine to disjoint or. (PR #76981)

[Nikita Popov via llvm-commits]

nikic wrote:

> @nikic Did you mean it will cause register allocator to introduce more spills?

Yeah. And as constant offset in GEP + load/store is usually part of the addressing mode and as such "free", we don't really gain anything by hoisting them out of the loop.

https://github.com/llvm/llvm-project/pull/76981