[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

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``````````bash
git-clang-format --diff 45651c357ae4e39a115bae6a936151b1741abf70 becbe3a324aa8b484a539cb5e07ea1caf6db5e11 -- llvm/unittests/ExecutionEngine/JITLink/JITLinkAArch32.inc llvm/utils/TableGen/JITLinkAArch32InstrInfo.cpp llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h llvm/lib/ExecutionEngine/JITLink/aarch32.cpp llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
index a0c25b5677..20a1051ef6 100644
--- a/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
+++ b/llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
@@ -226,7 +226,6 @@ template <> struct FixupInfo<Thumb_Call> : public FixupInfoThumb {
   static constexpr uint16_t LoBitNoBlx = 0x1000;
 };
 
-
 /// Helper function to read the initial addend for Data-class relocations.
 Expected<int64_t> readAddendData(LinkGraph &G, Block &B, Edge::OffsetT Offset,
                                  Edge::Kind Kind);
diff --git a/llvm/unittests/ExecutionEngine/JITLink/JITLinkAArch32.inc b/llvm/unittests/ExecutionEngine/JITLink/JITLinkAArch32.inc
index 42ef979592..aaff38b8c5 100644
--- a/llvm/unittests/ExecutionEngine/JITLink/JITLinkAArch32.inc
+++ b/llvm/unittests/ExecutionEngine/JITLink/JITLinkAArch32.inc
@@ -12,47 +12,47 @@ namespace llvm {
 namespace jitlink {
 namespace aarch32 {
 template <> struct FixupInfo<Arm_MovwAbsNC> : public FixupInfoArm {
-    static constexpr uint32_t Opcode = 0x3000000;
-    static constexpr uint32_t OpcodeMask = 0xff00000;
-    static constexpr uint32_t ImmMask = 0xf0fff;
-    static constexpr uint32_t RegMask = 0xf000;
+  static constexpr uint32_t Opcode = 0x3000000;
+  static constexpr uint32_t OpcodeMask = 0xff00000;
+  static constexpr uint32_t ImmMask = 0xf0fff;
+  static constexpr uint32_t RegMask = 0xf000;
 };
 
 template <> struct FixupInfo<Arm_MovtAbs> : public FixupInfoArm {
-    static constexpr uint32_t Opcode = 0x3400000;
-    static constexpr uint32_t OpcodeMask = 0xff00000;
-    static constexpr uint32_t ImmMask = 0xf0fff;
-    static constexpr uint32_t RegMask = 0xf000;
+  static constexpr uint32_t Opcode = 0x3400000;
+  static constexpr uint32_t OpcodeMask = 0xff00000;
+  static constexpr uint32_t ImmMask = 0xf0fff;
+  static constexpr uint32_t RegMask = 0xf000;
 };
 
 template <> struct FixupInfo<Thumb_MovwAbsNC> : public FixupInfoThumb {
-    static constexpr HalfWords Opcode {0xf240, 0x0};
-    static constexpr HalfWords OpcodeMask {0xfbf0, 0x8000};
-    static constexpr HalfWords ImmMask {0x40f, 0x70ff};
-    static constexpr HalfWords RegMask {0x0, 0xf00};
+  static constexpr HalfWords Opcode{0xf240, 0x0};
+  static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
+  static constexpr HalfWords ImmMask{0x40f, 0x70ff};
+  static constexpr HalfWords RegMask{0x0, 0xf00};
 };
 
 template <> struct FixupInfo<Thumb_MovtAbs> : public FixupInfoThumb {
-    static constexpr HalfWords Opcode {0xf2c0, 0x0};
-    static constexpr HalfWords OpcodeMask {0xfbf0, 0x8000};
-    static constexpr HalfWords ImmMask {0x40f, 0x70ff};
-    static constexpr HalfWords RegMask {0x0, 0xf00};
+  static constexpr HalfWords Opcode{0xf2c0, 0x0};
+  static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
+  static constexpr HalfWords ImmMask{0x40f, 0x70ff};
+  static constexpr HalfWords RegMask{0x0, 0xf00};
 };
 
 template <> struct FixupInfo<Thumb_MovwPrelNC> : public FixupInfoThumb {
-    static constexpr HalfWords Opcode {0xf240, 0x0};
-    static constexpr HalfWords OpcodeMask {0xfbf0, 0x8000};
-    static constexpr HalfWords ImmMask {0x40f, 0x70ff};
-    static constexpr HalfWords RegMask {0x0, 0xf00};
+  static constexpr HalfWords Opcode{0xf240, 0x0};
+  static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
+  static constexpr HalfWords ImmMask{0x40f, 0x70ff};
+  static constexpr HalfWords RegMask{0x0, 0xf00};
 };
 
 template <> struct FixupInfo<Thumb_MovtPrel> : public FixupInfoThumb {
-    static constexpr HalfWords Opcode {0xf2c0, 0x0};
-    static constexpr HalfWords OpcodeMask {0xfbf0, 0x8000};
-    static constexpr HalfWords ImmMask {0x40f, 0x70ff};
-    static constexpr HalfWords RegMask {0x0, 0xf00};
+  static constexpr HalfWords Opcode{0xf2c0, 0x0};
+  static constexpr HalfWords OpcodeMask{0xfbf0, 0x8000};
+  static constexpr HalfWords ImmMask{0x40f, 0x70ff};
+  static constexpr HalfWords RegMask{0x0, 0xf00};
 };
 
-} //aarch32
-} //jitlink
-} //llvm
+} // namespace aarch32
+} // namespace jitlink
+} // namespace llvm

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https://github.com/llvm/llvm-project/pull/76996