[llvm] [SimplifyCFG] Fold `switch(zext/sext(X))` into `switch(X)` (PR #76988)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 10:57:15 PST 2024
https://github.com/dtcxzyw created https://github.com/llvm/llvm-project/pull/76988
This patch folds `switch(zext/sext(X))` into `switch(X)`.
The original motivation of this patch is to optimize a pattern found in cvc5. For example:
```
%bf.load.i = load i16, ptr %d_kind.i, align 8
%bf.clear.i = and i16 %bf.load.i, 1023
%bf.cast.i = zext nneg i16 %bf.clear.i to i32
switch i32 %bf.cast.i, label %if.else [
i32 335, label %if.then
i32 303, label %if.then
]
if.then: ; preds = %entry, %entry
%d_children.i.i = getelementptr inbounds %"class.cvc5::internal::expr::NodeValue", ptr %0, i64 0, i32 3
%cmp.i.i.i.i.i = icmp eq i16 %bf.clear.i, 1023
%cond.i.i.i.i.i = select i1 %cmp.i.i.i.i.i, i32 -1, i32 %bf.cast.i
```
`%cmp.i.i.i.i.i` always evaluates to false because `%bf.clear.i` can only be 335 or 303.
Folding `switch i32 %bf.cast.i` to `switch i16 %bf.clear.i` will help `CVP` to handle this case.
See also https://github.com/llvm/llvm-project/pull/76928#issuecomment-1877055722.
>From e861ab44a02901614ea38181f0617b7d61e813c2 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 5 Jan 2024 02:41:56 +0800
Subject: [PATCH 1/2] [SimplifyCFG] Add pre-commit tests. NFC.
---
.../SimplifyCFG/switch-simplify-cond.ll | 159 ++++++++++++++++++
1 file changed, 159 insertions(+)
create mode 100644 llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
diff --git a/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll b/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
new file mode 100644
index 00000000000000..b22077d054ef61
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
@@ -0,0 +1,159 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt %s -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
+
+define i1 @test_switch_with_zext(i16 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: define i1 @test_switch_with_zext(
+; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
+; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i32 38, label [[COMMON_RET]]
+; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: ]
+; CHECK: common.ret:
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
+; CHECK: sw.default:
+; CHECK-NEXT: br label [[COMMON_RET]]
+;
+entry:
+ %a.ext = zext i16 %a to i32
+ switch i32 %a.ext, label %sw.default [
+ i32 37, label %sw.bb
+ i32 38, label %sw.bb
+ i32 39, label %sw.bb
+ ]
+
+sw.bb:
+ ret i1 %b
+sw.default:
+ ret i1 %c
+}
+
+define i1 @test_switch_with_sext(i16 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: define i1 @test_switch_with_sext(
+; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
+; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i32 38, label [[COMMON_RET]]
+; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: ]
+; CHECK: common.ret:
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
+; CHECK: sw.default:
+; CHECK-NEXT: br label [[COMMON_RET]]
+;
+entry:
+ %a.ext = sext i16 %a to i32
+ switch i32 %a.ext, label %sw.default [
+ i32 37, label %sw.bb
+ i32 38, label %sw.bb
+ i32 39, label %sw.bb
+ ]
+
+sw.bb:
+ ret i1 %b
+sw.default:
+ ret i1 %c
+}
+
+define i1 @test_switch_with_zext_unreachable_case(i16 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: define i1 @test_switch_with_zext_unreachable_case(
+; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
+; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i32 38, label [[COMMON_RET]]
+; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: ]
+; CHECK: common.ret:
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
+; CHECK: sw.default:
+; CHECK-NEXT: br label [[COMMON_RET]]
+;
+entry:
+ %a.ext = zext i16 %a to i32
+ switch i32 %a.ext, label %sw.default [
+ i32 37, label %sw.bb
+ i32 38, label %sw.bb
+ i32 39, label %sw.bb
+ i32 65537, label %sw.bb
+ ]
+
+sw.bb:
+ ret i1 %b
+sw.default:
+ ret i1 %c
+}
+
+define i1 @test_switch_with_sext_unreachable_case(i16 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: define i1 @test_switch_with_sext_unreachable_case(
+; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
+; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i32 38, label [[COMMON_RET]]
+; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: ]
+; CHECK: common.ret:
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
+; CHECK: sw.default:
+; CHECK-NEXT: br label [[COMMON_RET]]
+;
+entry:
+ %a.ext = sext i16 %a to i32
+ switch i32 %a.ext, label %sw.default [
+ i32 37, label %sw.bb
+ i32 38, label %sw.bb
+ i32 39, label %sw.bb
+ i32 -65537, label %sw.bb
+ ]
+
+sw.bb:
+ ret i1 %b
+sw.default:
+ ret i1 %c
+}
+
+define i1 @test_switch_with_zext_prof_preserve(i16 %a, i1 %b, i1 %c) {
+; CHECK-LABEL: define i1 @test_switch_with_zext_prof_preserve(
+; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
+; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i32 38, label [[COMMON_RET]]
+; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: ], !prof [[PROF0:![0-9]+]]
+; CHECK: common.ret:
+; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
+; CHECK: sw.default:
+; CHECK-NEXT: br label [[COMMON_RET]]
+;
+entry:
+ %a.ext = zext i16 %a to i32
+ switch i32 %a.ext, label %sw.default [
+ i32 37, label %sw.bb
+ i32 38, label %sw.bb
+ i32 39, label %sw.bb
+ ], !prof !0
+
+sw.bb:
+ ret i1 %b
+sw.default:
+ ret i1 %c
+}
+
+!0 = !{!"branch_weights", i32 8, i32 4, i32 2, i32 1}
+;.
+; CHECK: [[PROF0]] = !{!"branch_weights", i32 8, i32 4, i32 2, i32 1}
+;.
>From b37b69c3ad12dd24abe593355ad14aa324d7dd41 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Fri, 5 Jan 2024 02:49:01 +0800
Subject: [PATCH 2/2] [SimplifyCFG] Fold `switch(zext/sext(X))` into
`switch(X)`
---
llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 34 ++++++++++++++++
.../suppress-zero-branch-weights.ll | 10 ++---
.../SimplifyCFG/switch-masked-bits.ll | 10 ++---
.../SimplifyCFG/switch-simplify-cond.ll | 40 +++++++++----------
4 files changed, 64 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 61d891d65346bd..399153b442f936 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -7009,6 +7009,37 @@ static bool simplifySwitchOfPowersOfTwo(SwitchInst *SI, IRBuilder<> &Builder,
return true;
}
+// Fold switch(zext/sext(X)) into switch(X) if possible.
+static bool simplifySwitchCondition(SwitchInst *SI) {
+ Value *X;
+ if (match(SI->getCondition(), m_ZExtOrSExt(m_Value(X)))) {
+ SwitchInst *NewSI = SwitchInst::Create(X, SI->getDefaultDest(),
+ SI->getNumCases(), SI->getParent());
+ SwitchInstProfUpdateWrapper SIW(*SI);
+ SwitchInstProfUpdateWrapper NewSIW(*NewSI);
+ NewSI->setDebugLoc(SI->getDebugLoc());
+ NewSIW.setSuccessorWeight(0, SIW.getSuccessorWeight(0));
+
+ Type *SrcTy = X->getType();
+ unsigned SrcBW = SrcTy->getScalarSizeInBits();
+ for (auto &Case : SI->cases()) {
+ const APInt &CaseVal = Case.getCaseValue()->getValue();
+ assert(
+ (isa<ZExtInst>(SI->getCondition()) ? CaseVal.isIntN(SrcBW)
+ : CaseVal.isSignedIntN(SrcBW)) &&
+ "Unreachable cases should be eliminated by eliminateDeadSwitchCases");
+ APInt TruncVal = CaseVal.trunc(SrcBW);
+ NewSIW.addCase(cast<ConstantInt>(ConstantInt::get(SrcTy, TruncVal)),
+ Case.getCaseSuccessor(),
+ SIW.getSuccessorWeight(Case.getSuccessorIndex()));
+ }
+ SI->eraseFromParent();
+ return true;
+ }
+
+ return false;
+}
+
bool SimplifyCFGOpt::simplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) {
BasicBlock *BB = SI->getParent();
@@ -7041,6 +7072,9 @@ bool SimplifyCFGOpt::simplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) {
if (eliminateDeadSwitchCases(SI, DTU, Options.AC, DL))
return requestResimplify();
+ if (simplifySwitchCondition(SI))
+ return requestResimplify();
+
if (trySwitchToSelect(SI, Builder, DTU, DL, TTI))
return requestResimplify();
diff --git a/llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll b/llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll
index fd30b6352f7d41..2355f3987b8924 100644
--- a/llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll
+++ b/llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll
@@ -11,11 +11,11 @@ define i1 @repeated_signbits(i8 %condition) {
; CHECK-LABEL: @repeated_signbits(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
-; CHECK-NEXT: switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT: i32 0, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 127, label [[COMMON_RET]]
-; CHECK-NEXT: i32 -128, label [[COMMON_RET]]
-; CHECK-NEXT: i32 -1, label [[COMMON_RET]]
+; CHECK-NEXT: switch i8 [[CONDITION]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT: i8 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i8 127, label [[COMMON_RET]]
+; CHECK-NEXT: i8 -128, label [[COMMON_RET]]
+; CHECK-NEXT: i8 -1, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
diff --git a/llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll b/llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll
index f66240e9f4f7d4..0a0523aeb08ede 100644
--- a/llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll
+++ b/llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll
@@ -50,11 +50,11 @@ define i1 @repeated_signbits(i8 %condition) {
; CHECK-LABEL: @repeated_signbits(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
-; CHECK-NEXT: switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT: i32 0, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 127, label [[COMMON_RET]]
-; CHECK-NEXT: i32 -128, label [[COMMON_RET]]
-; CHECK-NEXT: i32 -1, label [[COMMON_RET]]
+; CHECK-NEXT: switch i8 [[CONDITION]], label [[DEFAULT:%.*]] [
+; CHECK-NEXT: i8 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i8 127, label [[COMMON_RET]]
+; CHECK-NEXT: i8 -128, label [[COMMON_RET]]
+; CHECK-NEXT: i8 -1, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
diff --git a/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll b/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
index b22077d054ef61..b0172d83fdbf03 100644
--- a/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
+++ b/llvm/test/Transforms/SimplifyCFG/switch-simplify-cond.ll
@@ -6,10 +6,10 @@ define i1 @test_switch_with_zext(i16 %a, i1 %b, i1 %c) {
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
-; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
-; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 38, label [[COMMON_RET]]
-; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i16 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i16 38, label [[COMMON_RET]]
+; CHECK-NEXT: i16 39, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
@@ -36,10 +36,10 @@ define i1 @test_switch_with_sext(i16 %a, i1 %b, i1 %c) {
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
-; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
-; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 38, label [[COMMON_RET]]
-; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i16 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i16 38, label [[COMMON_RET]]
+; CHECK-NEXT: i16 39, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
@@ -66,10 +66,10 @@ define i1 @test_switch_with_zext_unreachable_case(i16 %a, i1 %b, i1 %c) {
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
-; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
-; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 38, label [[COMMON_RET]]
-; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i16 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i16 38, label [[COMMON_RET]]
+; CHECK-NEXT: i16 39, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
@@ -97,10 +97,10 @@ define i1 @test_switch_with_sext_unreachable_case(i16 %a, i1 %b, i1 %c) {
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_EXT:%.*]] = sext i16 [[A]] to i32
-; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
-; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 38, label [[COMMON_RET]]
-; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i16 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i16 38, label [[COMMON_RET]]
+; CHECK-NEXT: i16 39, label [[COMMON_RET]]
; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
@@ -128,10 +128,10 @@ define i1 @test_switch_with_zext_prof_preserve(i16 %a, i1 %b, i1 %c) {
; CHECK-SAME: i16 [[A:%.*]], i1 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_EXT:%.*]] = zext i16 [[A]] to i32
-; CHECK-NEXT: switch i32 [[A_EXT]], label [[SW_DEFAULT:%.*]] [
-; CHECK-NEXT: i32 37, label [[COMMON_RET:%.*]]
-; CHECK-NEXT: i32 38, label [[COMMON_RET]]
-; CHECK-NEXT: i32 39, label [[COMMON_RET]]
+; CHECK-NEXT: switch i16 [[A]], label [[SW_DEFAULT:%.*]] [
+; CHECK-NEXT: i16 37, label [[COMMON_RET:%.*]]
+; CHECK-NEXT: i16 38, label [[COMMON_RET]]
+; CHECK-NEXT: i16 39, label [[COMMON_RET]]
; CHECK-NEXT: ], !prof [[PROF0:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[C]], [[SW_DEFAULT]] ], [ [[B]], [[ENTRY:%.*]] ], [ [[B]], [[ENTRY]] ], [ [[B]], [[ENTRY]] ]
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