[llvm] [RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (PR #76869)

[Wang Pengcheng via llvm-commits]

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@@ -0,0 +1,361 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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wangpc-pp wrote:

Yes, please go ahead!

https://github.com/llvm/llvm-project/pull/76869