[llvm] [RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (PR #76922)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 4 08:20:06 PST 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/76922
>From 90a29ac6da6f637515d2d28a933ef2645159f42e Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 4 Jan 2024 00:43:31 -0800
Subject: [PATCH 1/3] [RISCV] Remove incomplete PRE_DEC/POST_DEC code for
XTHeadMemIdx.
As far as I can tell if getIndexedAddressParts received an ISD::SUB,
the constant would be negated. So IsInc should be set to true since
the SUB was effectively converted to ADD. This means we should never
use PRE_DEC/POST_DEC.
No tests are affected because DAGCombine aggressively turns SUB with
constant into ADD so no lit test has a SUB reach getIndexedAddressParts.
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 10 ++++------
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 6 +++---
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index bfa3bf3cc74e2b..befa9e1159bef1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -763,14 +763,12 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
return false;
EVT LoadVT = Ld->getMemoryVT();
- bool IsPre = (AM == ISD::PRE_INC || AM == ISD::PRE_DEC);
- bool IsPost = (AM == ISD::POST_INC || AM == ISD::POST_DEC);
+ assert(AM == ISD::PRE_INC || AM == ISD::POST_INC &&
+ "Unexpected addressing mode");
+ bool IsPre = AM == ISD::PRE_INC;
+ bool IsPost = AM == ISD::POST_INC;
int64_t Offset = C->getSExtValue();
- // Convert decrements to increments by a negative quantity.
- if (AM == ISD::PRE_DEC || AM == ISD::POST_DEC)
- Offset = -Offset;
-
// The constants that can be encoded in the THeadMemIdx instructions
// are of the form (sign_extend(imm5) << imm2).
int64_t Shift;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index c8a94adcd91c6a..0a886fe70eeaed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1350,8 +1350,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
if (Subtarget.hasVendorXTHeadMemIdx()) {
- for (unsigned im = (unsigned)ISD::PRE_INC; im != (unsigned)ISD::POST_DEC;
- ++im) {
+ for (unsigned im : {ISD::PRE_INC, ISD::POST_INC}) {
setIndexedLoadAction(im, MVT::i8, Legal);
setIndexedStoreAction(im, MVT::i8, Legal);
setIndexedLoadAction(im, MVT::i16, Legal);
@@ -19288,7 +19287,8 @@ bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
if (!isLegalIndexedOffset)
return false;
- IsInc = (Op->getOpcode() == ISD::ADD);
+ // Constant for SUB was negated earlier.
+ IsInc = true;
Offset = Op->getOperand(1);
return true;
}
>From 2a0bfc7a4a92bfdc0d6c4a99e2b4cdbf288b994b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 4 Jan 2024 08:12:48 -0800
Subject: [PATCH 2/3] fixup! clang-format
---
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index befa9e1159bef1..7257c2e8fe1f69 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -763,8 +763,8 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
return false;
EVT LoadVT = Ld->getMemoryVT();
- assert(AM == ISD::PRE_INC || AM == ISD::POST_INC &&
- "Unexpected addressing mode");
+ assert(AM == ISD::PRE_INC ||
+ AM == ISD::POST_INC && "Unexpected addressing mode");
bool IsPre = AM == ISD::PRE_INC;
bool IsPost = AM == ISD::POST_INC;
int64_t Offset = C->getSExtValue();
>From 0d767857a03668ff83df336a4da12c6142f077b8 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 4 Jan 2024 08:19:29 -0800
Subject: [PATCH 3/3] fixup! Remove IsInc.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 13 ++++---------
llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 +--
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0a886fe70eeaed..7f48278be7c725 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -19260,7 +19260,6 @@ bool RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo() const {
bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
- bool &IsInc,
SelectionDAG &DAG) const {
// Target does not support indexed loads.
if (!Subtarget.hasVendorXTHeadMemIdx())
@@ -19287,8 +19286,6 @@ bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
if (!isLegalIndexedOffset)
return false;
- // Constant for SUB was negated earlier.
- IsInc = true;
Offset = Op->getOperand(1);
return true;
}
@@ -19311,11 +19308,10 @@ bool RISCVTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
} else
return false;
- bool IsInc;
- if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
+ if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, DAG))
return false;
- AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
+ AM = ISD::PRE_INC;
return true;
}
@@ -19335,15 +19331,14 @@ bool RISCVTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
} else
return false;
- bool IsInc;
- if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
+ if (!getIndexedAddressParts(Op, Base, Offset, AM, DAG))
return false;
// Post-indexing updates the base, so it's not a valid transform
// if that's not the same as the load's pointer.
if (Ptr != Base)
return false;
- AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
+ AM = ISD::POST_INC;
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index eacae8a700584c..4f6d0a4619401f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -773,8 +773,7 @@ class RISCVTargetLowering : public TargetLowering {
bool isVScaleKnownToBeAPowerOfTwo() const override;
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
- ISD::MemIndexedMode &AM, bool &IsInc,
- SelectionDAG &DAG) const;
+ ISD::MemIndexedMode &AM, SelectionDAG &DAG) const;
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override;
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