[llvm] [RISCV] Codegen support for XCVmem extension (PR #76916)

[Craig Topper via llvm-commits]

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@@ -19324,6 +19334,26 @@ bool RISCVTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                                      SDValue &Offset,
                                                      ISD::MemIndexedMode &AM,
                                                      SelectionDAG &DAG) const {
+  if (Subtarget.hasVendorXCVmem()) {
+    if (Op->getOpcode() != ISD::ADD)
+      return false;
+
+    if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
+      Base = LS->getBasePtr();
+    } else {
+      return false;
+    }
+
+    if (Base == Op->getOperand(0)) {
+      Offset = Op->getOperand(1);
+    } else if (Base == Op->getOperand(1)) {
+      Offset = Op->getOperand(0);
+    } else {
+      return false;
+    }
+    AM = ISD::POST_INC;
+    return true;
+  }
   EVT VT;
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topperc wrote:

Add blank line here

https://github.com/llvm/llvm-project/pull/76916