[llvm] [Cygwin] Cygwin X86ISelDAGToDAG.cpp 2 (PR #76883)

[徐持恒 Xu Chiheng via llvm-commits]

https://github.com/xu-chiheng updated https://github.com/llvm/llvm-project/pull/76883

>From 5a1f2bae0dd2c4282fce24299e41b9d0e3c104b7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
 <chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 16:09:59 +0800
Subject: [PATCH 1/3] 1

---
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 77a997588c4fee..8cbb0fd25e2ffe 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1828,7 +1828,9 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
   // That signifies access to globals that are known to be "near",
   // such as the GOT itself.
   CodeModel::Model M = TM.getCodeModel();
-  if (Subtarget->is64Bit() && M == CodeModel::Large && !IsRIPRelTLS)
+  if (Subtarget->is64Bit() && ((M == CodeModel::Large && !IsRIPRelTLS) ||
+                               (Subtarget->isTargetWindowsCygwin() &&
+                                M == CodeModel::Medium && !IsRIPRel)))
     return true;
 
   // Base and index reg must be 0 in order to use %rip as base.

>From 8d3b3ae4a09295ff98c359baa73aed6cba66e199 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
 <chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 18:36:42 +0800
Subject: [PATCH 2/3] 1

---
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 8cbb0fd25e2ffe..d6ec89f0515eab 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1833,6 +1833,7 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
                                 M == CodeModel::Medium && !IsRIPRel)))
     return true;
 
+
   // Base and index reg must be 0 in order to use %rip as base.
   if (IsRIPRel && AM.hasBaseOrIndexReg())
     return true;

>From c7e6516c32b04fcd69f68a279b58f7cd101b9249 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
 <chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 18:37:33 +0800
Subject: [PATCH 3/3] 1

---
 llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index d6ec89f0515eab..8cbb0fd25e2ffe 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1833,7 +1833,6 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
                                 M == CodeModel::Medium && !IsRIPRel)))
     return true;
 
-
   // Base and index reg must be 0 in order to use %rip as base.
   if (IsRIPRel && AM.hasBaseOrIndexReg())
     return true;