[llvm] [CodeGen][MachinePipeliner] Limit register pressure when scheduling (PR #74807)

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git-clang-format --diff 5ac12951b4e9bbfcc5791282d0961ec2b65575e9 1d2b6438a6f29b0665de0aba23f52f7c06affc33 -- llvm/include/llvm/CodeGen/MachinePipeliner.h llvm/lib/CodeGen/MachinePipeliner.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 0f154bc859..6004dfe5ec 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -2332,8 +2332,8 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
 /// Create an instruction stream that represents a single iteration and stage of
 /// each instruction. This function differs from SMSchedule::finalizeSchedule in
 /// that this doesn't have any side-effect to SwingSchedulerDAG. That is, this
-/// function is an approximation of SMSchedule::finalizeSchedule with all non-const
-/// operations removed.
+/// function is an approximation of SMSchedule::finalizeSchedule with all
+/// non-const operations removed.
 static void computeScheduledInsts(const SwingSchedulerDAG *SSD,
                                   SMSchedule &Schedule,
                                   std::vector<MachineInstr *> &OrderedInsts,

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https://github.com/llvm/llvm-project/pull/74807