[llvm] [PowerPC] make LR/LR8 CTR/CTR8 aliased (PR #76926)

[Chen Zheng via llvm-commits]

https://github.com/chenzheng1030 created https://github.com/llvm/llvm-project/pull/76926

fixes https://github.com/llvm/llvm-project/issues/47156 https://github.com/llvm/llvm-project/issues/47155

>From 6541695e4b0589c56ce15817fed7250c77936f62 Mon Sep 17 00:00:00 2001
From: Chen Zheng <czhengsz at cn.ibm.com>
Date: Thu, 4 Jan 2024 04:06:23 -0500
Subject: [PATCH] [PowerPC] make LR/LR8 CTR/CTR8 aliased

---
 llvm/lib/Target/PowerPC/PPCRegisterInfo.td |  9 ++++++---
 llvm/test/CodeGen/PowerPC/pr47155-47156.ll | 12 ++++++++----
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 375e63654db118..8a37e40414eeea 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -270,12 +270,15 @@ def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
 
 // Link register
 def LR  : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
-//let Aliases = [LR] in
-def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
+def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]> {
+  let Aliases = [LR];
+}
 
 // Count register
 def CTR  : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
-def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
+def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]> {
+  let Aliases = [CTR];
+}
 
 // VRsave register
 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
diff --git a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
index 26aa92e83f7af4..02f287634578a3 100644
--- a/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47155-47156.ll
@@ -9,9 +9,11 @@ define void @pr47155() {
 ; CHECK-NEXT: pr47155:%bb.0 entry
 ; CHECK:      SU(0):   INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr
 ; CHECK:      Successors:
+; CHECK-NEXT:   SU(1): Out  Latency=0
 ; CHECK-NEXT:   SU(1): Ord  Latency=0 Barrier
 ; CHECK-NEXT: SU(1):   INLINEASM &"mtlr 31"{{.*}}implicit-def early-clobber $lr8
 ; CHECK:      Predecessors:
+; CHECK-NEXT:   SU(0): Out  Latency=0
 ; CHECK-NEXT:   SU(0): Ord  Latency=0 Barrier
 ; CHECK-NEXT: ExitSU:
 entry:
@@ -25,11 +27,13 @@ define void @pr47156(ptr %fn) {
 ; CHECK: ********** MI Scheduling **********
 ; CHECK-NEXT: pr47156:%bb.0 entry
 ; CHECK:      SU(0):   INLINEASM &"mtctr 31"{{.*}}implicit-def early-clobber $ctr
-; CHECK-NOT:  Successors:
-; CHECK-NOT:  Predecessors:
-; CHECK:      SU(1):   MTCTR8 renamable $x3, implicit-def $ctr8
 ; CHECK:      Successors:
-; CHECK-NEXT: ExitSU:
+; CHECK-NEXT:   SU(1): Out  Latency=0
+; CHECK-NEXT: SU(1):   MTCTR8 renamable $x3, implicit-def $ctr8
+; CHECK:      Predecessors:
+; CHECK-NEXT:   SU(0): Out  Latency=0
+; CHECK-NEXT: Successors:
+; CHECK-NEXT:  ExitSU:
 ; CHECK-NEXT: SU(2):
 entry:
   call void asm sideeffect "mtctr 31", "~{ctr}"()