[llvm] [RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (PR #76922)

[via llvm-commits]

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``````````bash
git-clang-format --diff 8c72ff716b3e4b298695fa3faf6add860c6dbcb2 90a29ac6da6f637515d2d28a933ef2645159f42e -- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index befa9e1159..7257c2e8fe 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -763,8 +763,8 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
     return false;
 
   EVT LoadVT = Ld->getMemoryVT();
-  assert(AM == ISD::PRE_INC || AM == ISD::POST_INC &&
-         "Unexpected addressing mode");
+  assert(AM == ISD::PRE_INC ||
+         AM == ISD::POST_INC && "Unexpected addressing mode");
   bool IsPre = AM == ISD::PRE_INC;
   bool IsPost = AM == ISD::POST_INC;
   int64_t Offset = C->getSExtValue();

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https://github.com/llvm/llvm-project/pull/76922