[llvm] [Cygwin] Cygwin X86ISelDAGToDAG.cpp (PR #76883)
εΎζζ Xu Chiheng via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 3 23:55:25 PST 2024
https://github.com/xu-chiheng updated https://github.com/llvm/llvm-project/pull/76883
>From e56b6f7601c2f9056339d6c4d878cbba2eeb4631 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
<chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 09:15:08 +0800
Subject: [PATCH 1/3] 1
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 77a997588c4fee..7277baa509a0e7 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1828,7 +1828,9 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
// That signifies access to globals that are known to be "near",
// such as the GOT itself.
CodeModel::Model M = TM.getCodeModel();
- if (Subtarget->is64Bit() && M == CodeModel::Large && !IsRIPRelTLS)
+ if (Subtarget->is64Bit() &&
+ ((M == CodeModel::Large && !IsRIPRelTLS) ||
+ (M == CodeModel::Medium && !IsRIPRel)))
return true;
// Base and index reg must be 0 in order to use %rip as base.
>From baab67919a1d80a46875409647673bb3c01fecd0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
<chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 09:24:02 +0800
Subject: [PATCH 2/3] 1
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index 7277baa509a0e7..c152e755f7535c 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1828,9 +1828,8 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
// That signifies access to globals that are known to be "near",
// such as the GOT itself.
CodeModel::Model M = TM.getCodeModel();
- if (Subtarget->is64Bit() &&
- ((M == CodeModel::Large && !IsRIPRelTLS) ||
- (M == CodeModel::Medium && !IsRIPRel)))
+ if (Subtarget->is64Bit() && ((M == CodeModel::Large && !IsRIPRelTLS) ||
+ (M == CodeModel::Medium && !IsRIPRel)))
return true;
// Base and index reg must be 0 in order to use %rip as base.
>From 3d4dc7ead13383a7f1612655b0b41ae307842567 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E5=BE=90=E6=8C=81=E6=81=92=20Xu=20Chiheng?=
<chiheng.xu at gmail.com>
Date: Thu, 4 Jan 2024 15:55:04 +0800
Subject: [PATCH 3/3] 1
---
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
index c152e755f7535c..c2801ae6e874a3 100644
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1829,7 +1829,7 @@ bool X86DAGToDAGISel::matchWrapper(SDValue N, X86ISelAddressMode &AM) {
// such as the GOT itself.
CodeModel::Model M = TM.getCodeModel();
if (Subtarget->is64Bit() && ((M == CodeModel::Large && !IsRIPRelTLS) ||
- (M == CodeModel::Medium && !IsRIPRel)))
+ (Subtarget->isTargetWindowsCygwin() && M == CodeModel::Medium && !IsRIPRel)))
return true;
// Base and index reg must be 0 in order to use %rip as base.
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