[llvm] [RISCV] Codegen support for XCVmem extension (PR #76916)

[Craig Topper via llvm-commits]

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@@ -1417,6 +1417,67 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
   case ISD::LOAD: {
     if (tryIndexedLoad(Node))
       return;
+
+    if (Subtarget->hasVendorXCVmem()) {
+      // We hase to match post-incrementing load here
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topperc wrote:

hase?

https://github.com/llvm/llvm-project/pull/76916