[llvm] [RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (PR #76869)

[Wang Pengcheng via llvm-commits]

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+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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wangpc-pp wrote:

I am kind of confused on how these MCA tests are organized.

We have `llvm/test/tools/llvm-mca/RISCV/vle-vse.s`, but why is this `strided-load-store.s` test put under `lvm/test/tools/llvm-mca/RISCV/SiFive7`? They should test similar things I think.

If we want to put CPU (or schedule model) specific tests in its own directory, then we should move `llvm/test/tools/llvm-mca/RISCV/*` to `lvm/test/tools/llvm-mca/RISCV/SiFive7`?

https://github.com/llvm/llvm-project/pull/76869