[llvm] dd9681f - [X86][MC] Support encoding/decoding for APX variant INC/DEC/ADCX/ADOX instructions (#76721)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 3 18:12:16 PST 2024
Author: Shengchen Kan
Date: 2024-01-04T10:12:12+08:00
New Revision: dd9681f839c23e9caa6c495fb5a0df3625715348
URL: https://github.com/llvm/llvm-project/commit/dd9681f839c23e9caa6c495fb5a0df3625715348
DIFF: https://github.com/llvm/llvm-project/commit/dd9681f839c23e9caa6c495fb5a0df3625715348.diff
LOG: [X86][MC] Support encoding/decoding for APX variant INC/DEC/ADCX/ADOX instructions (#76721)
Four variants: promoted legacy, ND (new data destination), NF (no flags
update) and NF_ND (NF + ND).
The syntax of NF instructions is aligned with GNU binutils.
https://sourceware.org/pipermail/binutils/2023-September/129545.html
Added:
llvm/test/MC/Disassembler/X86/apx/adx.txt
llvm/test/MC/Disassembler/X86/apx/dec.txt
llvm/test/MC/Disassembler/X86/apx/inc.txt
llvm/test/MC/X86/apx/adx-att.s
llvm/test/MC/X86/apx/adx-intel.s
llvm/test/MC/X86/apx/dec-att.s
llvm/test/MC/X86/apx/dec-intel.s
llvm/test/MC/X86/apx/inc-att.s
llvm/test/MC/X86/apx/inc-intel.s
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86InstrUtils.td
llvm/test/TableGen/x86-fold-tables.inc
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 924956295e7c60..f7c361393fea62 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -1650,6 +1650,9 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
++SrcRegNum;
+ if (IsND) // Skip new data destination
+ ++CurOp;
+
emitRegModRMByte(MI.getOperand(SrcRegNum),
getX86RegNum(MI.getOperand(CurOp)), CB);
CurOp = SrcRegNum + 1;
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 08f5a8860b84ac..ed9f45bdd9d150 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -184,52 +184,139 @@ def IMUL64rmi32 : IMulOpMI_R<Xi64, WriteIMul64Imm>;
//===----------------------------------------------------------------------===//
// INC and DEC Instructions
//
-class IncOpR_RF<X86TypeInfo t> : UnaryOpR_RF<0xFF, MRM0r, "inc", t, null_frag> {
+class IncOpR_RF<X86TypeInfo t, bit ndd = 0> : UnaryOpR_RF<0xFF, MRM0r, "inc", t, null_frag, ndd> {
let Pattern = [(set t.RegClass:$dst, EFLAGS,
(X86add_flag_nocf t.RegClass:$src1, 1))];
}
-class DecOpR_RF<X86TypeInfo t> : UnaryOpR_RF<0xFF, MRM1r, "dec", t, null_frag> {
+class DecOpR_RF<X86TypeInfo t, bit ndd = 0> : UnaryOpR_RF<0xFF, MRM1r, "dec", t, null_frag, ndd> {
let Pattern = [(set t.RegClass:$dst, EFLAGS,
(X86sub_flag_nocf t.RegClass:$src1, 1))];
}
-class IncOpM_M<X86TypeInfo t> : UnaryOpM_MF<0xFF, MRM0m, "inc", t, null_frag> {
+class IncOpR_R<X86TypeInfo t, bit ndd = 0> : UnaryOpR_R<0xFF, MRM0r, "inc", t, null_frag, ndd>;
+class DecOpR_R<X86TypeInfo t, bit ndd = 0> : UnaryOpR_R<0xFF, MRM1r, "dec", t, null_frag, ndd>;
+class IncOpM_MF<X86TypeInfo t> : UnaryOpM_MF<0xFF, MRM0m, "inc", t, null_frag> {
let Pattern = [(store (add (t.LoadNode addr:$src1), 1), addr:$src1),
(implicit EFLAGS)];
}
-class DecOpM_M<X86TypeInfo t> : UnaryOpM_MF<0xFF, MRM1m, "dec", t, null_frag> {
+class DecOpM_MF<X86TypeInfo t> : UnaryOpM_MF<0xFF, MRM1m, "dec", t, null_frag> {
let Pattern = [(store (add (t.LoadNode addr:$src1), -1), addr:$src1),
(implicit EFLAGS)];
}
+class IncOpM_RF<X86TypeInfo t> : UnaryOpM_RF<0xFF, MRM0m, "inc", t, null_frag> {
+ let Pattern = [(set t.RegClass:$dst, EFLAGS, (add (t.LoadNode addr:$src1), 1))];
+}
+class DecOpM_RF<X86TypeInfo t> : UnaryOpM_RF<0xFF, MRM1m, "dec", t, null_frag> {
+ let Pattern = [(set t.RegClass:$dst, EFLAGS, (add (t.LoadNode addr:$src1), -1))];
+}
+class IncOpM_M<X86TypeInfo t> : UnaryOpM_M<0xFF, MRM0m, "inc", t, null_frag>;
+class DecOpM_M<X86TypeInfo t> : UnaryOpM_M<0xFF, MRM1m, "dec", t, null_frag>;
+class IncOpM_R<X86TypeInfo t> : UnaryOpM_R<0xFF, MRM0m, "inc", t, null_frag>;
+class DecOpM_R<X86TypeInfo t> : UnaryOpM_R<0xFF, MRM1m, "dec", t, null_frag>;
+
// IncDec_Alt - Instructions like "inc reg" short forms.
// Short forms only valid in 32-bit mode. Selected during MCInst lowering.
class IncDec_Alt<bits<8> o, string m, X86TypeInfo t>
: UnaryOpR_RF<o, AddRegFrm, m, t, null_frag>, Requires<[Not64BitMode]>;
let isConvertibleToThreeAddress = 1 in {
-def INC16r_alt : IncDec_Alt<0x40, "inc", Xi16>, OpSize16;
-def INC32r_alt : IncDec_Alt<0x40, "inc", Xi32>, OpSize32;
-def DEC16r_alt : IncDec_Alt<0x48, "dec", Xi16>, OpSize16;
-def DEC32r_alt : IncDec_Alt<0x48, "dec", Xi32>, OpSize32;
-def INC8r : IncOpR_RF<Xi8>;
-def INC16r : IncOpR_RF<Xi16>, OpSize16;
-def INC32r : IncOpR_RF<Xi32>, OpSize32;
-def INC64r : IncOpR_RF<Xi64>;
-def DEC8r : DecOpR_RF<Xi8>;
-def DEC16r : DecOpR_RF<Xi16>, OpSize16;
-def DEC32r : DecOpR_RF<Xi32>, OpSize32;
-def DEC64r : DecOpR_RF<Xi64>;
+ def INC16r_alt : IncDec_Alt<0x40, "inc", Xi16>, OpSize16;
+ def INC32r_alt : IncDec_Alt<0x40, "inc", Xi32>, OpSize32;
+ def DEC16r_alt : IncDec_Alt<0x48, "dec", Xi16>, OpSize16;
+ def DEC32r_alt : IncDec_Alt<0x48, "dec", Xi32>, OpSize32;
+ let Predicates = [NoNDD] in {
+ def INC8r : IncOpR_RF<Xi8>;
+ def INC16r : IncOpR_RF<Xi16>, OpSize16;
+ def INC32r : IncOpR_RF<Xi32>, OpSize32;
+ def INC64r : IncOpR_RF<Xi64>;
+ def DEC8r : DecOpR_RF<Xi8>;
+ def DEC16r : DecOpR_RF<Xi16>, OpSize16;
+ def DEC32r : DecOpR_RF<Xi32>, OpSize32;
+ def DEC64r : DecOpR_RF<Xi64>;
+ }
+ let Predicates = [HasNDD, In64BitMode] in {
+ def INC8r_ND : IncOpR_RF<Xi8, 1>;
+ def INC16r_ND : IncOpR_RF<Xi16, 1>, PD;
+ def INC32r_ND : IncOpR_RF<Xi32, 1>;
+ def INC64r_ND : IncOpR_RF<Xi64, 1>;
+ def DEC8r_ND : DecOpR_RF<Xi8, 1>;
+ def DEC16r_ND : DecOpR_RF<Xi16, 1>, PD;
+ def DEC32r_ND : DecOpR_RF<Xi32, 1>;
+ def DEC64r_ND : DecOpR_RF<Xi64, 1>;
+ }
+ let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
+ def INC8r_NF : IncOpR_R<Xi8>, NF;
+ def INC16r_NF : IncOpR_R<Xi16>, NF, PD;
+ def INC32r_NF : IncOpR_R<Xi32>, NF;
+ def INC64r_NF : IncOpR_R<Xi64>, NF;
+ def DEC8r_NF : DecOpR_R<Xi8>, NF;
+ def DEC16r_NF : DecOpR_R<Xi16>, NF, PD;
+ def DEC32r_NF : DecOpR_R<Xi32>, NF;
+ def DEC64r_NF : DecOpR_R<Xi64>, NF;
+ def INC8r_NF_ND : IncOpR_R<Xi8, 1>, NF;
+ def INC16r_NF_ND : IncOpR_R<Xi16, 1>, NF, PD;
+ def INC32r_NF_ND : IncOpR_R<Xi32, 1>, NF;
+ def INC64r_NF_ND : IncOpR_R<Xi64, 1>, NF;
+ def DEC8r_NF_ND : DecOpR_R<Xi8, 1>, NF;
+ def DEC16r_NF_ND : DecOpR_R<Xi16, 1>, NF, PD;
+ def DEC32r_NF_ND : DecOpR_R<Xi32, 1>, NF;
+ def DEC64r_NF_ND : DecOpR_R<Xi64, 1>, NF;
+ def INC8r_EVEX : IncOpR_RF<Xi8>, PL;
+ def INC16r_EVEX : IncOpR_RF<Xi16>, PL, PD;
+ def INC32r_EVEX : IncOpR_RF<Xi32>, PL;
+ def INC64r_EVEX : IncOpR_RF<Xi64>, PL;
+ def DEC8r_EVEX : DecOpR_RF<Xi8>, PL;
+ def DEC16r_EVEX : DecOpR_RF<Xi16>, PL, PD;
+ def DEC32r_EVEX : DecOpR_RF<Xi32>, PL;
+ def DEC64r_EVEX : DecOpR_RF<Xi64>, PL;
+ }
}
let Predicates = [UseIncDec] in {
-def INC8m : IncOpM_M<Xi8>;
-def INC16m : IncOpM_M<Xi16>, OpSize16;
-def INC32m : IncOpM_M<Xi32>, OpSize32;
-def DEC8m : DecOpM_M<Xi8>;
-def DEC16m : DecOpM_M<Xi16>, OpSize16;
-def DEC32m : DecOpM_M<Xi32>, OpSize32;
+ def INC8m : IncOpM_MF<Xi8>;
+ def INC16m : IncOpM_MF<Xi16>, OpSize16;
+ def INC32m : IncOpM_MF<Xi32>, OpSize32;
+ def DEC8m : DecOpM_MF<Xi8>;
+ def DEC16m : DecOpM_MF<Xi16>, OpSize16;
+ def DEC32m : DecOpM_MF<Xi32>, OpSize32;
}
let Predicates = [UseIncDec, In64BitMode] in {
-def INC64m : IncOpM_M<Xi64>;
-def DEC64m : DecOpM_M<Xi64>;
+ def INC64m : IncOpM_MF<Xi64>;
+ def DEC64m : DecOpM_MF<Xi64>;
+}
+let Predicates = [HasNDD, In64BitMode, UseIncDec] in {
+ def INC8m_ND : IncOpM_RF<Xi8>;
+ def INC16m_ND : IncOpM_RF<Xi16>, PD;
+ def INC32m_ND : IncOpM_RF<Xi32>;
+ def DEC8m_ND : DecOpM_RF<Xi8>;
+ def DEC16m_ND : DecOpM_RF<Xi16>, PD;
+ def DEC32m_ND : DecOpM_RF<Xi32>;
+ def INC64m_ND : IncOpM_RF<Xi64>;
+ def DEC64m_ND : DecOpM_RF<Xi64>;
+}
+let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
+ def INC8m_NF : IncOpM_M<Xi8>, NF;
+ def INC16m_NF : IncOpM_M<Xi16>, NF, PD;
+ def INC32m_NF : IncOpM_M<Xi32>, NF;
+ def INC64m_NF : IncOpM_M<Xi64>, NF;
+ def DEC8m_NF : DecOpM_M<Xi8>, NF;
+ def DEC16m_NF : DecOpM_M<Xi16>, NF, PD;
+ def DEC32m_NF : DecOpM_M<Xi32>, NF;
+ def DEC64m_NF : DecOpM_M<Xi64>, NF;
+ def INC8m_NF_ND : IncOpM_R<Xi8>, NF;
+ def INC16m_NF_ND : IncOpM_R<Xi16>, NF, PD;
+ def INC32m_NF_ND : IncOpM_R<Xi32>, NF;
+ def INC64m_NF_ND : IncOpM_R<Xi64>, NF;
+ def DEC8m_NF_ND : DecOpM_R<Xi8>, NF;
+ def DEC16m_NF_ND : DecOpM_R<Xi16>, NF, PD;
+ def DEC32m_NF_ND : DecOpM_R<Xi32>, NF;
+ def DEC64m_NF_ND : DecOpM_R<Xi64>, NF;
+ def INC8m_EVEX : IncOpM_MF<Xi8>, PL;
+ def INC16m_EVEX : IncOpM_MF<Xi16>, PL, PD;
+ def INC32m_EVEX : IncOpM_MF<Xi32>, PL;
+ def INC64m_EVEX : IncOpM_MF<Xi64>, PL;
+ def DEC8m_EVEX : DecOpM_MF<Xi8>, PL;
+ def DEC16m_EVEX : DecOpM_MF<Xi16>, PL, PD;
+ def DEC32m_EVEX : DecOpM_MF<Xi32>, PL;
+ def DEC64m_EVEX : DecOpM_MF<Xi64>, PL;
}
//===----------------------------------------------------------------------===//
@@ -1119,14 +1206,34 @@ defm MULX64 : MulX<Xi64, WriteMULX64>, REX_W;
// We don't have patterns for these as there is no advantage over ADC for
// most code.
let Form = MRMSrcReg in {
-def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
-def ADCX64rr : BinOpRRF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
-def ADOX32rr : BinOpRRF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
-def ADOX64rr : BinOpRRF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
+ def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32>, T8, PD;
+ def ADCX64rr : BinOpRRF_RF<0xF6, "adcx", Xi64>, T8, PD;
+ def ADOX32rr : BinOpRRF_RF<0xF6, "adox", Xi32>, T8, XS;
+ def ADOX64rr : BinOpRRF_RF<0xF6, "adox", Xi64>, T8, XS;
+ let Predicates =[In64BitMode] in {
+ def ADCX32rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
+ def ADCX64rr_EVEX : BinOpRRF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
+ def ADOX32rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
+ def ADOX64rr_EVEX : BinOpRRF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
+ def ADCX32rr_ND : BinOpRRF_RF<0x66, "adcx", Xi32, null_frag, 1>, PD;
+ def ADCX64rr_ND : BinOpRRF_RF<0x66, "adcx", Xi64, null_frag, 1>, PD;
+ def ADOX32rr_ND : BinOpRRF_RF<0x66, "adox", Xi32, null_frag, 1>, XS;
+ def ADOX64rr_ND : BinOpRRF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
+ }
}
let Form = MRMSrcMem in {
-def ADCX32rm : BinOpRMF_RF<0xF6, "adcx", Xi32, null_frag>, T8, PD;
-def ADCX64rm : BinOpRMF_RF<0xF6, "adcx", Xi64, null_frag>, T8, PD;
-def ADOX32rm : BinOpRMF_RF<0xF6, "adox", Xi32, null_frag>, T8, XS;
-def ADOX64rm : BinOpRMF_RF<0xF6, "adox", Xi64, null_frag>, T8, XS;
+ def ADCX32rm : BinOpRMF_RF<0xF6, "adcx", Xi32>, T8, PD;
+ def ADCX64rm : BinOpRMF_RF<0xF6, "adcx", Xi64>, T8, PD;
+ def ADOX32rm : BinOpRMF_RF<0xF6, "adox", Xi32>, T8, XS;
+ def ADOX64rm : BinOpRMF_RF<0xF6, "adox", Xi64>, T8, XS;
+ let Predicates =[In64BitMode] in {
+ def ADCX32rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi32>, EVEX, T_MAP4, PD;
+ def ADCX64rm_EVEX : BinOpRMF_RF<0x66, "adcx", Xi64>, EVEX, T_MAP4, PD;
+ def ADOX32rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi32>, EVEX, T_MAP4, XS;
+ def ADOX64rm_EVEX : BinOpRMF_RF<0x66, "adox", Xi64>, EVEX, T_MAP4, XS;
+ def ADCX32rm_ND : BinOpRMF_RF<0x66, "adcx", Xi32, null_frag, 1>, PD;
+ def ADCX64rm_ND : BinOpRMF_RF<0x66, "adcx", Xi64, null_frag, 1>, PD;
+ def ADOX32rm_ND : BinOpRMF_RF<0x66, "adox", Xi32, null_frag, 1>, XS;
+ def ADOX64rm_ND : BinOpRMF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
+ }
}
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
index da85922a018d64..132941a5734cca 100644
--- a/llvm/lib/Target/X86/X86InstrUtils.td
+++ b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -1005,7 +1005,7 @@ class BinOpRR_RF_Rev<bits<8> o, string m, X86TypeInfo t, bit ndd = 0>
}
// BinOpRRF_RF - Instructions that read "reg, reg", write "reg" and read/write
// EFLAGS.
-class BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
+class BinOpRRF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
: BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS,
(node t.RegClass:$src1, t.RegClass:$src2,
@@ -1041,7 +1041,7 @@ class BinOpRM_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit
(t.LoadNode addr:$src2)))]>, DefEFLAGS, NDD<ndd>;
// BinOpRMF_RF - Instructions that read "reg, [mem]", write "reg" and read/write
// EFLAGS.
-class BinOpRMF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node, bit ndd = 0>
+class BinOpRMF_RF<bits<8> o, string m, X86TypeInfo t, SDPatternOperator node = null_frag, bit ndd = 0>
: BinOpRM<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS,
(node t.RegClass:$src1, (t.LoadNode addr:$src2), EFLAGS))]>,
diff --git a/llvm/test/MC/Disassembler/X86/apx/adx.txt b/llvm/test/MC/Disassembler/X86/apx/adx.txt
new file mode 100644
index 00000000000000..926cd14bef1100
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/adx.txt
@@ -0,0 +1,66 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT: adcxl %r16d, %r17d
+# INTEL: adcx r17d, r16d
+0x62,0xec,0x7d,0x08,0x66,0xc8
+
+# ATT: adcxl %r16d, %r17d, %r18d
+# INTEL: adcx r18d, r17d, r16d
+0x62,0xec,0x6d,0x10,0x66,0xc8
+
+# ATT: adcxq %r16, %r17
+# INTEL: adcx r17, r16
+0x62,0xec,0xfd,0x08,0x66,0xc8
+
+# ATT: adcxq %r16, %r17, %r18
+# INTEL: adcx r18, r17, r16
+0x62,0xec,0xed,0x10,0x66,0xc8
+
+# ATT: adcxl (%r16), %r17d
+# INTEL: adcx r17d, dword ptr [r16]
+0x62,0xec,0x7d,0x08,0x66,0x08
+
+# ATT: adcxl (%r16), %r17d, %r18d
+# INTEL: adcx r18d, r17d, dword ptr [r16]
+0x62,0xec,0x6d,0x10,0x66,0x08
+
+# ATT: adcxq (%r16), %r17
+# INTEL: adcx r17, qword ptr [r16]
+0x62,0xec,0xfd,0x08,0x66,0x08
+
+# ATT: adcxq (%r16), %r17, %r18
+# INTEL: adcx r18, r17, qword ptr [r16]
+0x62,0xec,0xed,0x10,0x66,0x08
+
+# ATT: adoxl %r16d, %r17d
+# INTEL: adox r17d, r16d
+0x62,0xec,0x7e,0x08,0x66,0xc8
+
+# ATT: adoxl %r16d, %r17d, %r18d
+# INTEL: adox r18d, r17d, r16d
+0x62,0xec,0x6e,0x10,0x66,0xc8
+
+# ATT: adoxq %r16, %r17
+# INTEL: adox r17, r16
+0x62,0xec,0xfe,0x08,0x66,0xc8
+
+# ATT: adoxq %r16, %r17, %r18
+# INTEL: adox r18, r17, r16
+0x62,0xec,0xee,0x10,0x66,0xc8
+
+# ATT: adoxl (%r16), %r17d
+# INTEL: adox r17d, dword ptr [r16]
+0x62,0xec,0x7e,0x08,0x66,0x08
+
+# ATT: adoxl (%r16), %r17d, %r18d
+# INTEL: adox r18d, r17d, dword ptr [r16]
+0x62,0xec,0x6e,0x10,0x66,0x08
+
+# ATT: adoxq (%r16), %r17
+# INTEL: adox r17, qword ptr [r16]
+0x62,0xec,0xfe,0x08,0x66,0x08
+
+# ATT: adoxq (%r16), %r17, %r18
+# INTEL: adox r18, r17, qword ptr [r16]
+0x62,0xec,0xee,0x10,0x66,0x08
diff --git a/llvm/test/MC/Disassembler/X86/apx/dec.txt b/llvm/test/MC/Disassembler/X86/apx/dec.txt
new file mode 100644
index 00000000000000..029cf192558573
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/dec.txt
@@ -0,0 +1,130 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT: {evex} decb %bl
+# INTEL: {evex} dec bl
+0x62,0xf4,0x7c,0x08,0xfe,0xcb
+
+# ATT: {nf} decb %bl
+# INTEL: {nf} dec bl
+0x62,0xf4,0x7c,0x0c,0xfe,0xcb
+
+# ATT: decb %bl, %bl
+# INTEL: dec bl, bl
+0x62,0xf4,0x64,0x18,0xfe,0xcb
+
+# ATT: {nf} decb %bl, %bl
+# INTEL: {nf} dec bl, bl
+0x62,0xf4,0x64,0x1c,0xfe,0xcb
+
+# ATT: {evex} decw %dx
+# INTEL: {evex} dec dx
+0x62,0xf4,0x7d,0x08,0xff,0xca
+
+# ATT: {nf} decw %dx
+# INTEL: {nf} dec dx
+0x62,0xf4,0x7d,0x0c,0xff,0xca
+
+# ATT: decw %dx, %dx
+# INTEL: dec dx, dx
+0x62,0xf4,0x6d,0x18,0xff,0xca
+
+# ATT: {nf} decw %dx, %dx
+# INTEL: {nf} dec dx, dx
+0x62,0xf4,0x6d,0x1c,0xff,0xca
+
+# ATT: {evex} decl %ecx
+# INTEL: {evex} dec ecx
+0x62,0xf4,0x7c,0x08,0xff,0xc9
+
+# ATT: {nf} decl %ecx
+# INTEL: {nf} dec ecx
+0x62,0xf4,0x7c,0x0c,0xff,0xc9
+
+# ATT: decl %ecx, %ecx
+# INTEL: dec ecx, ecx
+0x62,0xf4,0x74,0x18,0xff,0xc9
+
+# ATT: {nf} decl %ecx, %ecx
+# INTEL: {nf} dec ecx, ecx
+0x62,0xf4,0x74,0x1c,0xff,0xc9
+
+# ATT: {evex} decq %r9
+# INTEL: {evex} dec r9
+0x62,0xd4,0xfc,0x08,0xff,0xc9
+
+# ATT: {nf} decq %r9
+# INTEL: {nf} dec r9
+0x62,0xd4,0xfc,0x0c,0xff,0xc9
+
+# ATT: decq %r9, %r9
+# INTEL: dec r9, r9
+0x62,0xd4,0xb4,0x18,0xff,0xc9
+
+# ATT: {nf} decq %r9, %r9
+# INTEL: {nf} dec r9, r9
+0x62,0xd4,0xb4,0x1c,0xff,0xc9
+
+# ATT: {evex} decb 291(%r8,%rax,4)
+# INTEL: {evex} dec byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x08,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decb 291(%r8,%rax,4)
+# INTEL: {nf} dec byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x0c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: decb 291(%r8,%rax,4), %bl
+# INTEL: dec bl, byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x64,0x18,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decb 291(%r8,%rax,4), %bl
+# INTEL: {nf} dec bl, byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x64,0x1c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} decw 291(%r8,%rax,4)
+# INTEL: {evex} dec word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7d,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decw 291(%r8,%rax,4)
+# INTEL: {nf} dec word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7d,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: decw 291(%r8,%rax,4), %dx
+# INTEL: dec dx, word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x6d,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decw 291(%r8,%rax,4), %dx
+# INTEL: {nf} dec dx, word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x6d,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} decl 291(%r8,%rax,4)
+# INTEL: {evex} dec dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decl 291(%r8,%rax,4)
+# INTEL: {nf} dec dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: decl 291(%r8,%rax,4), %ecx
+# INTEL: dec ecx, dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x74,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decl 291(%r8,%rax,4), %ecx
+# INTEL: {nf} dec ecx, dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x74,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} decq 291(%r8,%rax,4)
+# INTEL: {evex} dec qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xfc,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decq 291(%r8,%rax,4)
+# INTEL: {nf} dec qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xfc,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: decq 291(%r8,%rax,4), %r9
+# INTEL: dec r9, qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xb4,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} decq 291(%r8,%rax,4), %r9
+# INTEL: {nf} dec r9, qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xb4,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/Disassembler/X86/apx/inc.txt b/llvm/test/MC/Disassembler/X86/apx/inc.txt
new file mode 100644
index 00000000000000..0470319b4f6cdd
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/inc.txt
@@ -0,0 +1,130 @@
+# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT
+# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL
+
+# ATT: {evex} incb %bl
+# INTEL: {evex} inc bl
+0x62,0xf4,0x7c,0x08,0xfe,0xc3
+
+# ATT: {nf} incb %bl
+# INTEL: {nf} inc bl
+0x62,0xf4,0x7c,0x0c,0xfe,0xc3
+
+# ATT: incb %bl, %bl
+# INTEL: inc bl, bl
+0x62,0xf4,0x64,0x18,0xfe,0xc3
+
+# ATT: {nf} incb %bl, %bl
+# INTEL: {nf} inc bl, bl
+0x62,0xf4,0x64,0x1c,0xfe,0xc3
+
+# ATT: {evex} incw %dx
+# INTEL: {evex} inc dx
+0x62,0xf4,0x7d,0x08,0xff,0xc2
+
+# ATT: {nf} incw %dx
+# INTEL: {nf} inc dx
+0x62,0xf4,0x7d,0x0c,0xff,0xc2
+
+# ATT: incw %dx, %dx
+# INTEL: inc dx, dx
+0x62,0xf4,0x6d,0x18,0xff,0xc2
+
+# ATT: {nf} incw %dx, %dx
+# INTEL: {nf} inc dx, dx
+0x62,0xf4,0x6d,0x1c,0xff,0xc2
+
+# ATT: {evex} incl %ecx
+# INTEL: {evex} inc ecx
+0x62,0xf4,0x7c,0x08,0xff,0xc1
+
+# ATT: {nf} incl %ecx
+# INTEL: {nf} inc ecx
+0x62,0xf4,0x7c,0x0c,0xff,0xc1
+
+# ATT: incl %ecx, %ecx
+# INTEL: inc ecx, ecx
+0x62,0xf4,0x74,0x18,0xff,0xc1
+
+# ATT: {nf} incl %ecx, %ecx
+# INTEL: {nf} inc ecx, ecx
+0x62,0xf4,0x74,0x1c,0xff,0xc1
+
+# ATT: {evex} incq %r9
+# INTEL: {evex} inc r9
+0x62,0xd4,0xfc,0x08,0xff,0xc1
+
+# ATT: {nf} incq %r9
+# INTEL: {nf} inc r9
+0x62,0xd4,0xfc,0x0c,0xff,0xc1
+
+# ATT: incq %r9, %r9
+# INTEL: inc r9, r9
+0x62,0xd4,0xb4,0x18,0xff,0xc1
+
+# ATT: {nf} incq %r9, %r9
+# INTEL: {nf} inc r9, r9
+0x62,0xd4,0xb4,0x1c,0xff,0xc1
+
+# ATT: {evex} incb 291(%r8,%rax,4)
+# INTEL: {evex} inc byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x08,0xfe,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incb 291(%r8,%rax,4)
+# INTEL: {nf} inc byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x0c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: incb 291(%r8,%rax,4), %bl
+# INTEL: inc bl, byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x64,0x18,0xfe,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incb 291(%r8,%rax,4), %bl
+# INTEL: {nf} inc bl, byte ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x64,0x1c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} incw 291(%r8,%rax,4)
+# INTEL: {evex} inc word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7d,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incw 291(%r8,%rax,4)
+# INTEL: {nf} inc word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7d,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: incw 291(%r8,%rax,4), %dx
+# INTEL: inc dx, word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x6d,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incw 291(%r8,%rax,4), %dx
+# INTEL: {nf} inc dx, word ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x6d,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} incl 291(%r8,%rax,4)
+# INTEL: {evex} inc dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incl 291(%r8,%rax,4)
+# INTEL: {nf} inc dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x7c,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: incl 291(%r8,%rax,4), %ecx
+# INTEL: inc ecx, dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x74,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incl 291(%r8,%rax,4), %ecx
+# INTEL: {nf} inc ecx, dword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0x74,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {evex} incq 291(%r8,%rax,4)
+# INTEL: {evex} inc qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xfc,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incq 291(%r8,%rax,4)
+# INTEL: {nf} inc qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xfc,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: incq 291(%r8,%rax,4), %r9
+# INTEL: inc r9, qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xb4,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00
+
+# ATT: {nf} incq 291(%r8,%rax,4), %r9
+# INTEL: {nf} inc r9, qword ptr [r8 + 4*rax + 291]
+0x62,0xd4,0xb4,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/adx-att.s b/llvm/test/MC/X86/apx/adx-att.s
new file mode 100644
index 00000000000000..185d27897f8164
--- /dev/null
+++ b/llvm/test/MC/X86/apx/adx-att.s
@@ -0,0 +1,53 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-16: error:
+# ERROR-NOT: error:
+# CHECK: adcxl %r16d, %r17d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0x66,0xc8]
+ adcxl %r16d, %r17d
+# CHECK: adcxl %r16d, %r17d, %r18d
+# CHECK: encoding: [0x62,0xec,0x6d,0x10,0x66,0xc8]
+ adcxl %r16d, %r17d, %r18d
+# CHECK: adcxq %r16, %r17
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0x66,0xc8]
+ adcxq %r16, %r17
+# CHECK: adcxq %r16, %r17, %r18
+# CHECK: encoding: [0x62,0xec,0xed,0x10,0x66,0xc8]
+ adcxq %r16, %r17, %r18
+# CHECK: adcxl (%r16), %r17d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0x66,0x08]
+ adcxl (%r16), %r17d
+# CHECK: adcxl (%r16), %r17d, %r18d
+# CHECK: encoding: [0x62,0xec,0x6d,0x10,0x66,0x08]
+ adcxl (%r16), %r17d, %r18d
+# CHECK: adcxq (%r16), %r17
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0x66,0x08]
+ adcxq (%r16), %r17
+# CHECK: adcxq (%r16), %r17, %r18
+# CHECK: encoding: [0x62,0xec,0xed,0x10,0x66,0x08]
+ adcxq (%r16), %r17, %r18
+# CHECK: adoxl %r16d, %r17d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0x66,0xc8]
+ adoxl %r16d, %r17d
+# CHECK: adoxl %r16d, %r17d, %r18d
+# CHECK: encoding: [0x62,0xec,0x6e,0x10,0x66,0xc8]
+ adoxl %r16d, %r17d, %r18d
+# CHECK: adoxq %r16, %r17
+# CHECK: encoding: [0x62,0xec,0xfe,0x08,0x66,0xc8]
+ adoxq %r16, %r17
+# CHECK: adoxq %r16, %r17, %r18
+# CHECK: encoding: [0x62,0xec,0xee,0x10,0x66,0xc8]
+ adoxq %r16, %r17, %r18
+# CHECK: adoxl (%r16), %r17d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0x66,0x08]
+ adoxl (%r16), %r17d
+# CHECK: adoxl (%r16), %r17d, %r18d
+# CHECK: encoding: [0x62,0xec,0x6e,0x10,0x66,0x08]
+ adoxl (%r16), %r17d, %r18d
+# CHECK: adoxq (%r16), %r17
+# CHECK: encoding: [0x62,0xec,0xfe,0x08,0x66,0x08]
+ adoxq (%r16), %r17
+# CHECK: adoxq (%r16), %r17, %r18
+# CHECK: encoding: [0x62,0xec,0xee,0x10,0x66,0x08]
+ adoxq (%r16), %r17, %r18
diff --git a/llvm/test/MC/X86/apx/adx-intel.s b/llvm/test/MC/X86/apx/adx-intel.s
new file mode 100644
index 00000000000000..0cbe9df1852cce
--- /dev/null
+++ b/llvm/test/MC/X86/apx/adx-intel.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: adcx r17d, r16d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0x66,0xc8]
+ adcx r17d, r16d
+# CHECK: adcx r18d, r17d, r16d
+# CHECK: encoding: [0x62,0xec,0x6d,0x10,0x66,0xc8]
+ adcx r18d, r17d, r16d
+# CHECK: adcx r17, r16
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0x66,0xc8]
+ adcx r17, r16
+# CHECK: adcx r18, r17, r16
+# CHECK: encoding: [0x62,0xec,0xed,0x10,0x66,0xc8]
+ adcx r18, r17, r16
+# CHECK: adcx r17d, dword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0x66,0x08]
+ adcx r17d, dword ptr [r16]
+# CHECK: adcx r18d, r17d, dword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0x6d,0x10,0x66,0x08]
+ adcx r18d, r17d, dword ptr [r16]
+# CHECK: adcx r17, qword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0x66,0x08]
+ adcx r17, qword ptr [r16]
+# CHECK: adcx r18, r17, qword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0xed,0x10,0x66,0x08]
+ adcx r18, r17, qword ptr [r16]
+# CHECK: adox r17d, r16d
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0x66,0xc8]
+ adox r17d, r16d
+# CHECK: adox r18d, r17d, r16d
+# CHECK: encoding: [0x62,0xec,0x6e,0x10,0x66,0xc8]
+ adox r18d, r17d, r16d
+# CHECK: adox r17, r16
+# CHECK: encoding: [0x62,0xec,0xfe,0x08,0x66,0xc8]
+ adox r17, r16
+# CHECK: adox r18, r17, r16
+# CHECK: encoding: [0x62,0xec,0xee,0x10,0x66,0xc8]
+ adox r18, r17, r16
+# CHECK: adox r17d, dword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0x7e,0x08,0x66,0x08]
+ adox r17d, dword ptr [r16]
+# CHECK: adox r18d, r17d, dword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0x6e,0x10,0x66,0x08]
+ adox r18d, r17d, dword ptr [r16]
+# CHECK: adox r17, qword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0xfe,0x08,0x66,0x08]
+ adox r17, qword ptr [r16]
+# CHECK: adox r18, r17, qword ptr [r16]
+# CHECK: encoding: [0x62,0xec,0xee,0x10,0x66,0x08]
+ adox r18, r17, qword ptr [r16]
diff --git a/llvm/test/MC/X86/apx/dec-att.s b/llvm/test/MC/X86/apx/dec-att.s
new file mode 100644
index 00000000000000..a5d3cc49b11352
--- /dev/null
+++ b/llvm/test/MC/X86/apx/dec-att.s
@@ -0,0 +1,101 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-32: error:
+# ERROR-NOT: error:
+# CHECK: {evex} decb %bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xfe,0xcb]
+ {evex} decb %bl
+# CHECK: {nf} decb %bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xfe,0xcb]
+ {nf} decb %bl
+# CHECK: decb %bl, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xfe,0xcb]
+ decb %bl, %bl
+# CHECK: {nf} decb %bl, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xfe,0xcb]
+ {nf} decb %bl, %bl
+# CHECK: {evex} decw %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xff,0xca]
+ {evex} decw %dx
+# CHECK: {nf} decw %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xff,0xca]
+ {nf} decw %dx
+# CHECK: decw %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xff,0xca]
+ decw %dx, %dx
+# CHECK: {nf} decw %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xff,0xca]
+ {nf} decw %dx, %dx
+# CHECK: {evex} decl %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xff,0xc9]
+ {evex} decl %ecx
+# CHECK: {nf} decl %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xff,0xc9]
+ {nf} decl %ecx
+# CHECK: decl %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xff,0xc9]
+ decl %ecx, %ecx
+# CHECK: {nf} decl %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xff,0xc9]
+ {nf} decl %ecx, %ecx
+# CHECK: {evex} decq %r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0xc9]
+ {evex} decq %r9
+# CHECK: {nf} decq %r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0xc9]
+ {nf} decq %r9
+# CHECK: decq %r9, %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0xc9]
+ decq %r9, %r9
+# CHECK: {nf} decq %r9, %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0xc9]
+ {nf} decq %r9, %r9
+# CHECK: {evex} decb 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} decb 291(%r8,%rax,4)
+# CHECK: {nf} decb 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decb 291(%r8,%rax,4)
+# CHECK: decb 291(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ decb 291(%r8,%rax,4), %bl
+# CHECK: {nf} decb 291(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decb 291(%r8,%rax,4), %bl
+# CHECK: {evex} decw 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} decw 291(%r8,%rax,4)
+# CHECK: {nf} decw 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decw 291(%r8,%rax,4)
+# CHECK: decw 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x6d,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ decw 291(%r8,%rax,4), %dx
+# CHECK: {nf} decw 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x6d,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decw 291(%r8,%rax,4), %dx
+# CHECK: {evex} decl 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} decl 291(%r8,%rax,4)
+# CHECK: {nf} decl 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decl 291(%r8,%rax,4)
+# CHECK: decl 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x74,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ decl 291(%r8,%rax,4), %ecx
+# CHECK: {nf} decl 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x74,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decl 291(%r8,%rax,4), %ecx
+# CHECK: {evex} decq 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} decq 291(%r8,%rax,4)
+# CHECK: {nf} decq 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decq 291(%r8,%rax,4)
+# CHECK: decq 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ decq 291(%r8,%rax,4), %r9
+# CHECK: {nf} decq 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} decq 291(%r8,%rax,4), %r9
diff --git a/llvm/test/MC/X86/apx/dec-intel.s b/llvm/test/MC/X86/apx/dec-intel.s
new file mode 100644
index 00000000000000..5fde06d024efb5
--- /dev/null
+++ b/llvm/test/MC/X86/apx/dec-intel.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: {evex} dec bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xfe,0xcb]
+ {evex} dec bl
+# CHECK: {nf} dec bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xfe,0xcb]
+ {nf} dec bl
+# CHECK: dec bl, bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xfe,0xcb]
+ dec bl, bl
+# CHECK: {nf} dec bl, bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xfe,0xcb]
+ {nf} dec bl, bl
+# CHECK: {evex} dec dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xff,0xca]
+ {evex} dec dx
+# CHECK: {nf} dec dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xff,0xca]
+ {nf} dec dx
+# CHECK: dec dx, dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xff,0xca]
+ dec dx, dx
+# CHECK: {nf} dec dx, dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xff,0xca]
+ {nf} dec dx, dx
+# CHECK: {evex} dec ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xff,0xc9]
+ {evex} dec ecx
+# CHECK: {nf} dec ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xff,0xc9]
+ {nf} dec ecx
+# CHECK: dec ecx, ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xff,0xc9]
+ dec ecx, ecx
+# CHECK: {nf} dec ecx, ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xff,0xc9]
+ {nf} dec ecx, ecx
+# CHECK: {evex} dec r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0xc9]
+ {evex} dec r9
+# CHECK: {nf} dec r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0xc9]
+ {nf} dec r9
+# CHECK: dec r9, r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0xc9]
+ dec r9, r9
+# CHECK: {nf} dec r9, r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0xc9]
+ {nf} dec r9, r9
+# CHECK: {evex} dec byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} dec byte ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec byte ptr [r8 + 4*rax + 291]
+# CHECK: dec bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ dec bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xfe,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: {evex} dec word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} dec word ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec word ptr [r8 + 4*rax + 291]
+# CHECK: dec dx, word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x6d,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ dec dx, word ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec dx, word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x6d,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec dx, word ptr [r8 + 4*rax + 291]
+# CHECK: {evex} dec dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} dec dword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec dword ptr [r8 + 4*rax + 291]
+# CHECK: dec ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x74,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ dec ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x74,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: {evex} dec qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {evex} dec qword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec qword ptr [r8 + 4*rax + 291]
+# CHECK: dec r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ dec r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} dec r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0x8c,0x80,0x23,0x01,0x00,0x00]
+ {nf} dec r9, qword ptr [r8 + 4*rax + 291]
diff --git a/llvm/test/MC/X86/apx/inc-att.s b/llvm/test/MC/X86/apx/inc-att.s
new file mode 100644
index 00000000000000..5e08ae30894960
--- /dev/null
+++ b/llvm/test/MC/X86/apx/inc-att.s
@@ -0,0 +1,101 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-32: error:
+# ERROR-NOT: error:
+# CHECK: {evex} incb %bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xfe,0xc3]
+ {evex} incb %bl
+# CHECK: {nf} incb %bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xfe,0xc3]
+ {nf} incb %bl
+# CHECK: incb %bl, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xfe,0xc3]
+ incb %bl, %bl
+# CHECK: {nf} incb %bl, %bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xfe,0xc3]
+ {nf} incb %bl, %bl
+# CHECK: {evex} incw %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xff,0xc2]
+ {evex} incw %dx
+# CHECK: {nf} incw %dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xff,0xc2]
+ {nf} incw %dx
+# CHECK: incw %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xff,0xc2]
+ incw %dx, %dx
+# CHECK: {nf} incw %dx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xff,0xc2]
+ {nf} incw %dx, %dx
+# CHECK: {evex} incl %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xff,0xc1]
+ {evex} incl %ecx
+# CHECK: {nf} incl %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xff,0xc1]
+ {nf} incl %ecx
+# CHECK: incl %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xff,0xc1]
+ incl %ecx, %ecx
+# CHECK: {nf} incl %ecx, %ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xff,0xc1]
+ {nf} incl %ecx, %ecx
+# CHECK: {evex} incq %r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0xc1]
+ {evex} incq %r9
+# CHECK: {nf} incq %r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0xc1]
+ {nf} incq %r9
+# CHECK: incq %r9, %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0xc1]
+ incq %r9, %r9
+# CHECK: {nf} incq %r9, %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0xc1]
+ {nf} incq %r9, %r9
+# CHECK: {evex} incb 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} incb 291(%r8,%rax,4)
+# CHECK: {nf} incb 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incb 291(%r8,%rax,4)
+# CHECK: incb 291(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ incb 291(%r8,%rax,4), %bl
+# CHECK: {nf} incb 291(%r8,%rax,4), %bl
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incb 291(%r8,%rax,4), %bl
+# CHECK: {evex} incw 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} incw 291(%r8,%rax,4)
+# CHECK: {nf} incw 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incw 291(%r8,%rax,4)
+# CHECK: incw 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x6d,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ incw 291(%r8,%rax,4), %dx
+# CHECK: {nf} incw 291(%r8,%rax,4), %dx
+# CHECK: encoding: [0x62,0xd4,0x6d,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incw 291(%r8,%rax,4), %dx
+# CHECK: {evex} incl 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} incl 291(%r8,%rax,4)
+# CHECK: {nf} incl 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incl 291(%r8,%rax,4)
+# CHECK: incl 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x74,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ incl 291(%r8,%rax,4), %ecx
+# CHECK: {nf} incl 291(%r8,%rax,4), %ecx
+# CHECK: encoding: [0x62,0xd4,0x74,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incl 291(%r8,%rax,4), %ecx
+# CHECK: {evex} incq 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} incq 291(%r8,%rax,4)
+# CHECK: {nf} incq 291(%r8,%rax,4)
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incq 291(%r8,%rax,4)
+# CHECK: incq 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ incq 291(%r8,%rax,4), %r9
+# CHECK: {nf} incq 291(%r8,%rax,4), %r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} incq 291(%r8,%rax,4), %r9
diff --git a/llvm/test/MC/X86/apx/inc-intel.s b/llvm/test/MC/X86/apx/inc-intel.s
new file mode 100644
index 00000000000000..e35ce06433bd29
--- /dev/null
+++ b/llvm/test/MC/X86/apx/inc-intel.s
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s
+
+# CHECK: {evex} inc bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xfe,0xc3]
+ {evex} inc bl
+# CHECK: {nf} inc bl
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xfe,0xc3]
+ {nf} inc bl
+# CHECK: inc bl, bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x18,0xfe,0xc3]
+ inc bl, bl
+# CHECK: {nf} inc bl, bl
+# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xfe,0xc3]
+ {nf} inc bl, bl
+# CHECK: {evex} inc dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xff,0xc2]
+ {evex} inc dx
+# CHECK: {nf} inc dx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xff,0xc2]
+ {nf} inc dx
+# CHECK: inc dx, dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xff,0xc2]
+ inc dx, dx
+# CHECK: {nf} inc dx, dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xff,0xc2]
+ {nf} inc dx, dx
+# CHECK: {evex} inc ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xff,0xc1]
+ {evex} inc ecx
+# CHECK: {nf} inc ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xff,0xc1]
+ {nf} inc ecx
+# CHECK: inc ecx, ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xff,0xc1]
+ inc ecx, ecx
+# CHECK: {nf} inc ecx, ecx
+# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xff,0xc1]
+ {nf} inc ecx, ecx
+# CHECK: {evex} inc r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0xc1]
+ {evex} inc r9
+# CHECK: {nf} inc r9
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0xc1]
+ {nf} inc r9
+# CHECK: inc r9, r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0xc1]
+ inc r9, r9
+# CHECK: {nf} inc r9, r9
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0xc1]
+ {nf} inc r9, r9
+# CHECK: {evex} inc byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} inc byte ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc byte ptr [r8 + 4*rax + 291]
+# CHECK: inc bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x64,0x18,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ inc bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x64,0x1c,0xfe,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc bl, byte ptr [r8 + 4*rax + 291]
+# CHECK: {evex} inc word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} inc word ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc word ptr [r8 + 4*rax + 291]
+# CHECK: inc dx, word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x6d,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ inc dx, word ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc dx, word ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x6d,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc dx, word ptr [r8 + 4*rax + 291]
+# CHECK: {evex} inc dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} inc dword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc dword ptr [r8 + 4*rax + 291]
+# CHECK: inc ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x74,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ inc ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0x74,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc ecx, dword ptr [r8 + 4*rax + 291]
+# CHECK: {evex} inc qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {evex} inc qword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xfc,0x0c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc qword ptr [r8 + 4*rax + 291]
+# CHECK: inc r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ inc r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: {nf} inc r9, qword ptr [r8 + 4*rax + 291]
+# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xff,0x84,0x80,0x23,0x01,0x00,0x00]
+ {nf} inc r9, qword ptr [r8 + 4*rax + 291]
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 8ac46a5b669249..4e37285b08ba2e 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -75,13 +75,21 @@ static const X86FoldTableEntry Table2Addr[] = {
{X86::BTS32ri8, X86::BTS32mi8, TB_NO_REVERSE},
{X86::BTS64ri8, X86::BTS64mi8, TB_NO_REVERSE},
{X86::DEC16r, X86::DEC16m, TB_NO_REVERSE},
+ {X86::DEC16r_NF, X86::DEC16m_NF, TB_NO_REVERSE},
{X86::DEC32r, X86::DEC32m, TB_NO_REVERSE},
+ {X86::DEC32r_NF, X86::DEC32m_NF, TB_NO_REVERSE},
{X86::DEC64r, X86::DEC64m, TB_NO_REVERSE},
+ {X86::DEC64r_NF, X86::DEC64m_NF, TB_NO_REVERSE},
{X86::DEC8r, X86::DEC8m, TB_NO_REVERSE},
+ {X86::DEC8r_NF, X86::DEC8m_NF, TB_NO_REVERSE},
{X86::INC16r, X86::INC16m, TB_NO_REVERSE},
+ {X86::INC16r_NF, X86::INC16m_NF, TB_NO_REVERSE},
{X86::INC32r, X86::INC32m, TB_NO_REVERSE},
+ {X86::INC32r_NF, X86::INC32m_NF, TB_NO_REVERSE},
{X86::INC64r, X86::INC64m, TB_NO_REVERSE},
+ {X86::INC64r_NF, X86::INC64m_NF, TB_NO_REVERSE},
{X86::INC8r, X86::INC8m, TB_NO_REVERSE},
+ {X86::INC8r_NF, X86::INC8m_NF, TB_NO_REVERSE},
{X86::NEG16r, X86::NEG16m, TB_NO_REVERSE},
{X86::NEG16r_NF, X86::NEG16m_NF, TB_NO_REVERSE},
{X86::NEG32r, X86::NEG32m, TB_NO_REVERSE},
@@ -604,12 +612,28 @@ static const X86FoldTableEntry Table1[] = {
{X86::CVTTSS2SI64rr_Int, X86::CVTTSS2SI64rm_Int, TB_NO_REVERSE},
{X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0},
{X86::CVTTSS2SIrr_Int, X86::CVTTSS2SIrm_Int, TB_NO_REVERSE},
+ {X86::DEC16r_ND, X86::DEC16m_ND, 0},
+ {X86::DEC16r_NF_ND, X86::DEC16m_NF_ND, 0},
+ {X86::DEC32r_ND, X86::DEC32m_ND, 0},
+ {X86::DEC32r_NF_ND, X86::DEC32m_NF_ND, 0},
+ {X86::DEC64r_ND, X86::DEC64m_ND, 0},
+ {X86::DEC64r_NF_ND, X86::DEC64m_NF_ND, 0},
+ {X86::DEC8r_ND, X86::DEC8m_ND, 0},
+ {X86::DEC8r_NF_ND, X86::DEC8m_NF_ND, 0},
{X86::IMUL16rri, X86::IMUL16rmi, 0},
{X86::IMUL16rri8, X86::IMUL16rmi8, 0},
{X86::IMUL32rri, X86::IMUL32rmi, 0},
{X86::IMUL32rri8, X86::IMUL32rmi8, 0},
{X86::IMUL64rri32, X86::IMUL64rmi32, 0},
{X86::IMUL64rri8, X86::IMUL64rmi8, 0},
+ {X86::INC16r_ND, X86::INC16m_ND, 0},
+ {X86::INC16r_NF_ND, X86::INC16m_NF_ND, 0},
+ {X86::INC32r_ND, X86::INC32m_ND, 0},
+ {X86::INC32r_NF_ND, X86::INC32m_NF_ND, 0},
+ {X86::INC64r_ND, X86::INC64m_ND, 0},
+ {X86::INC64r_NF_ND, X86::INC64m_NF_ND, 0},
+ {X86::INC8r_ND, X86::INC8m_ND, 0},
+ {X86::INC8r_NF_ND, X86::INC8m_NF_ND, 0},
{X86::KMOVBkk, X86::KMOVBkm, TB_NO_REVERSE},
{X86::KMOVBkk_EVEX, X86::KMOVBkm_EVEX, TB_NO_REVERSE},
{X86::KMOVDkk, X86::KMOVDkm, 0},
@@ -1533,7 +1557,11 @@ static const X86FoldTableEntry Table2[] = {
{X86::ADC8rr, X86::ADC8rm, 0},
{X86::ADC8rr_ND, X86::ADC8rm_ND, 0},
{X86::ADCX32rr, X86::ADCX32rm, 0},
+ {X86::ADCX32rr_EVEX, X86::ADCX32rm_EVEX, 0},
+ {X86::ADCX32rr_ND, X86::ADCX32rm_ND, 0},
{X86::ADCX64rr, X86::ADCX64rm, 0},
+ {X86::ADCX64rr_EVEX, X86::ADCX64rm_EVEX, 0},
+ {X86::ADCX64rr_ND, X86::ADCX64rm_ND, 0},
{X86::ADD16rr, X86::ADD16rm, 0},
{X86::ADD16rr_ND, X86::ADD16rm_ND, 0},
{X86::ADD16rr_NF, X86::ADD16rm_NF, 0},
@@ -1559,7 +1587,11 @@ static const X86FoldTableEntry Table2[] = {
{X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16},
{X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16},
{X86::ADOX32rr, X86::ADOX32rm, 0},
+ {X86::ADOX32rr_EVEX, X86::ADOX32rm_EVEX, 0},
+ {X86::ADOX32rr_ND, X86::ADOX32rm_ND, 0},
{X86::ADOX64rr, X86::ADOX64rm, 0},
+ {X86::ADOX64rr_EVEX, X86::ADOX64rm_EVEX, 0},
+ {X86::ADOX64rr_ND, X86::ADOX64rm_ND, 0},
{X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16},
{X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16},
{X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16},
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