[llvm] 5fc712c - [AArch64] Add PMOV aliases with implicit portion index (#76056)
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Wed Jan 3 01:56:38 PST 2024
Author: Momchil Velikov
Date: 2024-01-03T09:56:34Z
New Revision: 5fc712c4bbe84e6cbaa1f7d2a0300f613f11b0c3
URL: https://github.com/llvm/llvm-project/commit/5fc712c4bbe84e6cbaa1f7d2a0300f613f11b0c3
DIFF: https://github.com/llvm/llvm-project/commit/5fc712c4bbe84e6cbaa1f7d2a0300f613f11b0c3.diff
LOG: [AArch64] Add PMOV aliases with implicit portion index (#76056)
In the latest ISA update the syntax of the PMOV instructions was updated
to allow the portion index to be optional, default to zero.
https://developer.arm.com/documentation/ddi0602/2023-09/SVE-Instructions/PMOV--to-predicate---Move-predicate-from-vector-?lang=en
https://developer.arm.com/documentation/ddi0602/2023-09/SVE-Instructions/PMOV--to-vector---Move-predicate-to-vector-?lang=en
Added:
Modified:
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/MC/AArch64/SVE2p1/pmov.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index b7552541e950d9..789ec817d3d8b8 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -10082,6 +10082,12 @@ multiclass sve2p1_vector_to_pred<string mnemonic, SDPatternOperator Op_lane, SDP
def : InstAlias<mnemonic # "\t$Pd, $Zn",
(!cast<Instruction>(NAME # _B) PPR8:$Pd, ZPRAny:$Zn, 0), 1>;
+ def : InstAlias<mnemonic # "\t$Pd, $Zn",
+ (!cast<Instruction>(NAME # _H) PPR16:$Pd, ZPRAny:$Zn, 0), 0>;
+ def : InstAlias<mnemonic # "\t$Pd, $Zn",
+ (!cast<Instruction>(NAME # _S) PPR32:$Pd, ZPRAny:$Zn, 0), 0>;
+ def : InstAlias<mnemonic # "\t$Pd, $Zn",
+ (!cast<Instruction>(NAME # _D) PPR64:$Pd, ZPRAny:$Zn, 0), 0>;
// any_lane
def : Pat<(nxv16i1 (Op_lane (nxv16i8 ZPRAny:$Zn), (i32 timm32_0_0:$Idx))),
@@ -10143,6 +10149,12 @@ multiclass sve2p1_pred_to_vector<string mnemonic, SDPatternOperator MergeOp,
def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
+ def : InstAlias<mnemonic # "\t$Zd, $Pn",
+ (!cast<Instruction>(NAME # _H) ZPRAny:$Zd, 0, PPR16:$Pn), 0>;
+ def : InstAlias<mnemonic # "\t$Zd, $Pn",
+ (!cast<Instruction>(NAME # _S) ZPRAny:$Zd, 0, PPR32:$Pn), 0>;
+ def : InstAlias<mnemonic # "\t$Zd, $Pn",
+ (!cast<Instruction>(NAME # _D) ZPRAny:$Zd, 0, PPR64:$Pn), 0>;
// Merge
def : Pat<(nxv8i16 (MergeOp (nxv8i16 ZPRAny:$Zd), (nxv8i1 PPR16:$Pn), (i32 timm32_1_1:$Idx))),
diff --git a/llvm/test/MC/AArch64/SVE2p1/pmov.s b/llvm/test/MC/AArch64/SVE2p1/pmov.s
index ca2b55b47c325a..8c08cf7e6441a5 100644
--- a/llvm/test/MC/AArch64/SVE2p1/pmov.s
+++ b/llvm/test/MC/AArch64/SVE2p1/pmov.s
@@ -20,6 +20,12 @@ pmov p0.h, z0[0] // 00000101-00101100-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052c3800 <unknown>
+pmov p0.h, z0 // 00000101-00101100-00111000-00000000
+// CHECK-INST: pmov p0.h, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0x2c,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052c3800 <unknown>
+
pmov p5.h, z10[0] // 00000101-00101100-00111001-01000101
// CHECK-INST: pmov p5.h, z10[0]
// CHECK-ENCODING: [0x45,0x39,0x2c,0x05]
@@ -44,6 +50,12 @@ pmov p0.s, z0[0] // 00000101-01101000-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05683800 <unknown>
+pmov p0.s, z0 // 00000101-01101000-00111000-00000000
+// CHECK-INST: pmov p0.s, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0x68,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05683800 <unknown>
+
pmov p5.s, z10[2] // 00000101-01101100-00111001-01000101
// CHECK-INST: pmov p5.s, z10[2]
// CHECK-ENCODING: [0x45,0x39,0x6c,0x05]
@@ -68,6 +80,12 @@ pmov p0.d, z0[0] // 00000101-10101000-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a83800 <unknown>
+pmov p0.d, z0 // 00000101-10101000-00111000-00000000
+// CHECK-INST: pmov p0.d, z0[0]
+// CHECK-ENCODING: [0x00,0x38,0xa8,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a83800 <unknown>
+
pmov p5.d, z10[6] // 00000101-11101100-00111001-01000101
// CHECK-INST: pmov p5.d, z10[6]
// CHECK-ENCODING: [0x45,0x39,0xec,0x05]
@@ -122,6 +140,12 @@ pmov z0[0], p0.h // 00000101-00101101-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 052d3800 <unknown>
+pmov z0, p0.h // 00000101-00101101-00111000-00000000
+// CHECK-INST: pmov z0[0], p0.h
+// CHECK-ENCODING: [0x00,0x38,0x2d,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 052d3800 <unknown>
+
pmov z21[0], p10.h // 00000101-00101101-00111001-01010101
// CHECK-INST: pmov z21[0], p10.h
// CHECK-ENCODING: [0x55,0x39,0x2d,0x05]
@@ -147,6 +171,12 @@ pmov z0[0], p0.s // 00000101-01101001-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05693800 <unknown>
+pmov z0, p0.s // 00000101-01101001-00111000-00000000
+// CHECK-INST: pmov z0[0], p0.s
+// CHECK-ENCODING: [0x00,0x38,0x69,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05693800 <unknown>
+
pmov z21[2], p10.s // 00000101-01101101-00111001-01010101
// CHECK-INST: pmov z21[2], p10.s
// CHECK-ENCODING: [0x55,0x39,0x6d,0x05]
@@ -171,6 +201,12 @@ pmov z0[0], p0.d // 00000101-10101001-00111000-00000000
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 05a93800 <unknown>
+pmov z0, p0.d // 00000101-10101001-00111000-00000000
+// CHECK-INST: pmov z0[0], p0.d
+// CHECK-ENCODING: [0x00,0x38,0xa9,0x05]
+// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
+// CHECK-UNKNOWN: 05a93800 <unknown>
+
pmov z21[6], p10.d // 00000101-11101101-00111001-01010101
// CHECK-INST: pmov z21[6], p10.d
// CHECK-ENCODING: [0x55,0x39,0xed,0x05]
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