[llvm] [AMDGPU] Prefer lower total register usage in regions with spilling (PR #71882)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> 3. (2 Excess VGPR, 0 Excess SGPR) is preferable to (1 Excess VGPR, 1 Excess SGPR) since the latter needs to insert more spill code.

This part doesn't entirely make sense to me. The SGPR spill code may end up larger, but could still be faster. Unless the spill-to-vgpr handling ends up inducing a VGPR spill, I'd spill expect to prefer an excess SGPR to excess VGPR

https://github.com/llvm/llvm-project/pull/71882