[llvm] [RISCV][GlobalISel] Legalize scalable vectorized G_ADD, G_SUB, G_AND, G_OR, and G_XOR (PR #71400)

Jiahan Xie via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 2 19:47:35 PST 2024

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https://github.com/jiahanxie353 edited https://github.com/llvm/llvm-project/pull/71400

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Next message: [llvm] 4e347b4 - Revert "[RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (#72340)"
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