[llvm] [X86][MC] Support Enc/Dec for NF for promoted BMI instructions in 73899 (PR #76709)
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Tue Jan 2 19:24:28 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc
Author: None (XinWang10)
<details>
<summary>Changes</summary>
---
Patch is 36.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/76709.diff
21 Files Affected:
- (modified) llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp (+16-1)
- (modified) llvm/lib/Target/X86/X86InstrArithmetic.td (+4)
- (modified) llvm/lib/Target/X86/X86InstrMisc.td (+23-3)
- (modified) llvm/test/MC/Disassembler/X86/apx/andn.txt (+32)
- (modified) llvm/test/MC/Disassembler/X86/apx/bextr.txt (+33)
- (modified) llvm/test/MC/Disassembler/X86/apx/blsi.txt (+32)
- (modified) llvm/test/MC/Disassembler/X86/apx/blsr.txt (+32)
- (modified) llvm/test/MC/Disassembler/X86/apx/bzhi.txt (+32)
- (modified) llvm/test/MC/X86/apx/andn-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/andn-intel.s (+32)
- (modified) llvm/test/MC/X86/apx/bextr-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/bextr-intel.s (+32)
- (modified) llvm/test/MC/X86/apx/blsi-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/blsi-intel.s (+32)
- (modified) llvm/test/MC/X86/apx/blsmsk-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/blsmsk-intel.s (+32)
- (modified) llvm/test/MC/X86/apx/blsr-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/blsr-intel.s (+32)
- (modified) llvm/test/MC/X86/apx/bzhi-att.s (+33-1)
- (modified) llvm/test/MC/X86/apx/bzhi-intel.s (+32)
- (modified) llvm/test/TableGen/x86-fold-tables.inc (+12)
``````````diff
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 347dc0d4ed43a7..12a4cc7e97544a 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -1134,6 +1134,21 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID,
return 0;
}
+static bool isNFnotMap4(InternalInstruction *insn) {
+ // Promoted BMI instrs below has nf version.
+ if (insn->opcodeType == THREEBYTE_38 &&
+ ppFromXOP3of3(insn->vectorExtensionPrefix[2]) == VEX_PREFIX_NONE) {
+ switch (insn->opcode) {
+ case 0xf2: // ANDN
+ case 0xf3: // BLSI, BLSR, BLSMSK
+ case 0xf5: // BZHI
+ case 0xf7: // BEXTR
+ return true;
+ }
+ }
+ return false;
+}
+
// Determine the ID of an instruction, consuming the ModR/M byte as appropriate
// for extended and escape opcodes. Determines the attributes and context for
// the instruction before doing so.
@@ -1171,7 +1186,7 @@ static int getInstructionID(struct InternalInstruction *insn,
attrMask |= ATTR_EVEXB;
// nf bit is the MSB of aaa
if (nfFromEVEX4of4(insn->vectorExtensionPrefix[3]) &&
- insn->opcodeType == MAP4)
+ (insn->opcodeType == MAP4 || isNFnotMap4(insn)))
attrMask |= ATTR_EVEXNF;
else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]))
attrMask |= ATTR_EVEXK;
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index 6b0c1b8c28c950..abfab1c31621d6 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1054,6 +1054,10 @@ defm ANDN32 : AndN<Xi32, "">, VEX, Requires<[HasBMI, NoEGPR]>;
defm ANDN64 : AndN<Xi64, "">, VEX, REX_W, Requires<[HasBMI, NoEGPR]>;
defm ANDN32 : AndN<Xi32, "_EVEX">, EVEX, Requires<[HasBMI, HasEGPR, In64BitMode]>;
defm ANDN64 : AndN<Xi64, "_EVEX">, EVEX, REX_W, Requires<[HasBMI, HasEGPR, In64BitMode]>;
+let Pattern = [(null_frag)] in {
+defm ANDN32 : AndN<Xi32, "_NF">, EVEX, EVEX_NF, Requires<[In64BitMode]>;
+defm ANDN64 : AndN<Xi64, "_NF">, EVEX, EVEX_NF, REX_W, Requires<[In64BitMode]>;
+}
}
let Predicates = [HasBMI], AddedComplexity = -6 in {
diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td
index 305bd74f7bd70a..d5ff9bf8e911be 100644
--- a/llvm/lib/Target/X86/X86InstrMisc.td
+++ b/llvm/lib/Target/X86/X86InstrMisc.td
@@ -1235,7 +1235,7 @@ let Predicates = [HasBMI, NoEGPR], Defs = [EFLAGS] in {
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, REX_W;
}
-let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in {
+let Predicates = [HasBMI, HasEGPR, In64BitMode], Defs = [EFLAGS] in {
defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX;
defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX;
defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS, "_EVEX">, EVEX;
@@ -1244,6 +1244,15 @@ let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in {
defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS, "_EVEX">, REX_W, EVEX;
}
+let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
+ defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS, "_NF">, EVEX, EVEX_NF;
+ defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS, "_NF">, REX_W, EVEX, EVEX_NF;
+ defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS, "_NF">, EVEX, EVEX_NF;
+ defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS, "_NF">, REX_W, EVEX, EVEX_NF;
+ defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS, "_NF">, EVEX, EVEX_NF;
+ defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS, "_NF">, REX_W, EVEX, EVEX_NF;
+}
+
let Predicates = [HasBMI] in {
// FIXME(1): patterns for the load versions are not implemented
// FIXME(2): By only matching `add_su` and `ineg_su` we may emit
@@ -1314,19 +1323,30 @@ let Predicates = [HasBMI2, NoEGPR], Defs = [EFLAGS] in {
defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem,
X86bzhi, loadi64, WriteBZHI>, REX_W;
}
-let Predicates = [HasBMI, HasEGPR], Defs = [EFLAGS] in {
+let Predicates = [HasBMI, HasEGPR, In64BitMode], Defs = [EFLAGS] in {
defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem,
X86bextr, loadi32, WriteBEXTR, "_EVEX">, EVEX;
defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem,
X86bextr, loadi64, WriteBEXTR, "_EVEX">, EVEX, REX_W;
}
-let Predicates = [HasBMI2, HasEGPR], Defs = [EFLAGS] in {
+let Predicates = [HasBMI2, HasEGPR, In64BitMode], Defs = [EFLAGS] in {
defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem,
X86bzhi, loadi32, WriteBZHI, "_EVEX">, EVEX;
defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem,
X86bzhi, loadi64, WriteBZHI, "_EVEX">, EVEX, REX_W;
}
+let Predicates = [In64BitMode], Pattern = [(null_frag)] in {
+ defm BEXTR32 : bmi4VOp3_base<0xF7, "bextr{l}", GR32, i32mem,
+ X86bextr, loadi32, WriteBEXTR, "_NF">, EVEX, EVEX_NF;
+ defm BEXTR64 : bmi4VOp3_base<0xF7, "bextr{q}", GR64, i64mem,
+ X86bextr, loadi64, WriteBEXTR, "_NF">, EVEX, EVEX_NF, REX_W;
+ defm BZHI32 : bmi4VOp3_base<0xF5, "bzhi{l}", GR32, i32mem,
+ X86bzhi, loadi32, WriteBZHI, "_NF">, EVEX, EVEX_NF;
+ defm BZHI64 : bmi4VOp3_base<0xF5, "bzhi{q}", GR64, i64mem,
+ X86bzhi, loadi64, WriteBZHI, "_NF">, EVEX, EVEX_NF, REX_W;
+}
+
def CountTrailingOnes : SDNodeXForm<imm, [{
// Count the trailing ones in the immediate.
return getI8Imm(llvm::countr_one(N->getZExtValue()), SDLoc(N));
diff --git a/llvm/test/MC/Disassembler/X86/apx/andn.txt b/llvm/test/MC/Disassembler/X86/apx/andn.txt
index 8b943d2a0ac44c..564b1c51920cec 100644
--- a/llvm/test/MC/Disassembler/X86/apx/andn.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/andn.txt
@@ -1,6 +1,38 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: {nf} andnl %ecx, %edx, %r10d
+# INTEL: {nf} andn r10d, edx, ecx
+0x62,0x72,0x6c,0x0c,0xf2,0xd1
+
+# ATT: andnl %ecx, %edx, %r10d
+# INTEL: andn r10d, edx, ecx
+0x62,0x72,0x6c,0x08,0xf2,0xd1
+
+# ATT: {nf} andnq %r9, %r15, %r11
+# INTEL: {nf} andn r11, r15, r9
+0x62,0x52,0x84,0x0c,0xf2,0xd9
+
+# ATT: andnq %r9, %r15, %r11
+# INTEL: andn r11, r15, r9
+0x62,0x52,0x84,0x08,0xf2,0xd9
+
+# ATT: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx
+# INTEL: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: andnl 123(%rax,%rbx,4), %ecx, %edx
+# INTEL: andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: {nf} andnq 123(%rax,%rbx,4), %r9, %r15
+# INTEL: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: andnq 123(%rax,%rbx,4), %r9, %r15
+# INTEL: andn r15, r9, qword ptr [rax + 4*rbx + 123]
+0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00
+
# ATT: andnl %r18d, %r22d, %r26d
# INTEL: andn r26d, r22d, r18d
0x62,0x6a,0x4c,0x00,0xf2,0xd2
diff --git a/llvm/test/MC/Disassembler/X86/apx/bextr.txt b/llvm/test/MC/Disassembler/X86/apx/bextr.txt
index abd92864b315e3..e5dfbbbdd5fa1b 100644
--- a/llvm/test/MC/Disassembler/X86/apx/bextr.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/bextr.txt
@@ -1,6 +1,39 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# CHECK: {nf} bextr r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2]
+ {nf} bextr r10d, edx, ecx
+
+# CHECK: bextr r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2]
+ bextr r10d, edx, ecx
+
+# CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+
+# CHECK: bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+
+# CHECK: {nf} bextr r11, r15, r9
+# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf]
+ {nf} bextr r11, r15, r9
+
+# CHECK: bextr r11, r15, r9
+# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf]
+ bextr r11, r15, r9
+
+# CHECK: {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {nf} bextr r15, qword ptr [rax + 4*rbx + 123], r9
+
+# CHECK: bextr r15, qword ptr [rax + 4*rbx + 123], r9
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ bextr r15, qword ptr [rax + 4*rbx + 123], r9
+
+
# ATT: bextrl %r18d, %r22d, %r26d
# INTEL: bextr r26d, r22d, r18d
0x62,0x6a,0x6c,0x00,0xf7,0xd6
diff --git a/llvm/test/MC/Disassembler/X86/apx/blsi.txt b/llvm/test/MC/Disassembler/X86/apx/blsi.txt
index 254ec90caea515..af984a8b7b6370 100644
--- a/llvm/test/MC/Disassembler/X86/apx/blsi.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/blsi.txt
@@ -1,6 +1,38 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: {nf} blsil %ecx, %edx
+# INTEL: {nf} blsi edx, ecx
+0x62,0xf2,0x6c,0x0c,0xf3,0xd9
+
+# ATT: blsil %ecx, %edx
+# INTEL: blsi edx, ecx
+0x62,0xf2,0x6c,0x08,0xf3,0xd9
+
+# ATT: {nf} blsiq %r9, %r15
+# INTEL: {nf} blsi r15, r9
+0x62,0xd2,0x84,0x0c,0xf3,0xd9
+
+# ATT: blsiq %r9, %r15
+# INTEL: blsi r15, r9
+0x62,0xd2,0x84,0x08,0xf3,0xd9
+
+# ATT: {nf} blsil 123(%rax,%rbx,4), %ecx
+# INTEL: {nf} blsi ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: blsil 123(%rax,%rbx,4), %ecx
+# INTEL: blsi ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: {nf} blsiq 123(%rax,%rbx,4), %r9
+# INTEL: {nf} blsi r9, qword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0xb4,0x0c,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: blsiq 123(%rax,%rbx,4), %r9
+# INTEL: blsi r9, qword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0xb4,0x08,0xf3,0x9c,0x98,0x7b,0x00,0x00,0x00
+
# ATT: blsil %r18d, %r22d
# INTEL: blsi r22d, r18d
0x62,0xfa,0x4c,0x00,0xf3,0xda
diff --git a/llvm/test/MC/Disassembler/X86/apx/blsr.txt b/llvm/test/MC/Disassembler/X86/apx/blsr.txt
index 37df4306da26ed..6f7874595aa7a5 100644
--- a/llvm/test/MC/Disassembler/X86/apx/blsr.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/blsr.txt
@@ -1,6 +1,38 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: {nf} blsrl %ecx, %edx
+# INTEL: {nf} blsr edx, ecx
+0x62,0xf2,0x6c,0x0c,0xf3,0xc9
+
+# ATT: blsrl %ecx, %edx
+# INTEL: blsr edx, ecx
+0x62,0xf2,0x6c,0x08,0xf3,0xc9
+
+# ATT: {nf} blsrq %r9, %r15
+# INTEL: {nf} blsr r15, r9
+0x62,0xd2,0x84,0x0c,0xf3,0xc9
+
+# ATT: blsrq %r9, %r15
+# INTEL: blsr r15, r9
+0x62,0xd2,0x84,0x08,0xf3,0xc9
+
+# ATT: {nf} blsrl 123(%rax,%rbx,4), %ecx
+# INTEL: {nf} blsr ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: blsrl 123(%rax,%rbx,4), %ecx
+# INTEL: blsr ecx, dword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0x74,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: {nf} blsrq 123(%rax,%rbx,4), %r9
+# INTEL: {nf} blsr r9, qword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0xb4,0x0c,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: blsrq 123(%rax,%rbx,4), %r9
+# INTEL: blsr r9, qword ptr [rax + 4*rbx + 123]
+0x62,0xf2,0xb4,0x08,0xf3,0x8c,0x98,0x7b,0x00,0x00,0x00
+
# ATT: blsrl %r18d, %r22d
# INTEL: blsr r22d, r18d
0x62,0xfa,0x4c,0x00,0xf3,0xca
diff --git a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt
index 44f496e3cc0840..8eec590b048786 100644
--- a/llvm/test/MC/Disassembler/X86/apx/bzhi.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/bzhi.txt
@@ -1,6 +1,38 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+# ATT: {nf} bzhil %ecx, %edx, %r10d
+# INTEL: {nf} bzhi r10d, edx, ecx
+0x62,0x72,0x74,0x0c,0xf5,0xd2
+
+# ATT: bzhil %ecx, %edx, %r10d
+# INTEL: bzhi r10d, edx, ecx
+0x62,0x72,0x74,0x08,0xf5,0xd2
+
+# ATT: {nf} bzhil %ecx, 123(%rax,%rbx,4), %edx
+# INTEL: {nf} bzhi edx, dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf2,0x74,0x0c,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: bzhil %ecx, 123(%rax,%rbx,4), %edx
+# INTEL: bzhi edx, dword ptr [rax + 4*rbx + 123], ecx
+0x62,0xf2,0x74,0x08,0xf5,0x94,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: {nf} bzhiq %r9, %r15, %r11
+# INTEL: {nf} bzhi r11, r15, r9
+0x62,0x52,0xb4,0x0c,0xf5,0xdf
+
+# ATT: bzhiq %r9, %r15, %r11
+# INTEL: bzhi r11, r15, r9
+0x62,0x52,0xb4,0x08,0xf5,0xdf
+
+# ATT: {nf} bzhiq %r9, 123(%rax,%rbx,4), %r15
+# INTEL: {nf} bzhi r15, qword ptr [rax + 4*rbx + 123], r9
+0x62,0x72,0xb4,0x0c,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00
+
+# ATT: bzhiq %r9, 123(%rax,%rbx,4), %r15
+# INTEL: bzhi r15, qword ptr [rax + 4*rbx + 123], r9
+0x62,0x72,0xb4,0x08,0xf5,0xbc,0x98,0x7b,0x00,0x00,0x00
+
# ATT: bzhil %r18d, %r22d, %r26d
# INTEL: bzhi r26d, r22d, r18d
0x62,0x6a,0x6c,0x00,0xf5,0xd6
diff --git a/llvm/test/MC/X86/apx/andn-att.s b/llvm/test/MC/X86/apx/andn-att.s
index d68cee8bcf1f72..f6ab0f0069ec09 100644
--- a/llvm/test/MC/X86/apx/andn-att.s
+++ b/llvm/test/MC/X86/apx/andn-att.s
@@ -1,8 +1,40 @@
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-# ERROR-COUNT-4: error:
+# ERROR-COUNT-12: error:
# ERROR-NOT: error:
+# CHECK: {nf} andnl %ecx, %edx, %r10d
+# CHECK: encoding: [0x62,0x72,0x6c,0x0c,0xf2,0xd1]
+ {nf} andnl %ecx, %edx, %r10d
+
+# CHECK: {evex} andnl %ecx, %edx, %r10d
+# CHECK: encoding: [0x62,0x72,0x6c,0x08,0xf2,0xd1]
+ {evex} andnl %ecx, %edx, %r10d
+
+# CHECK: {nf} andnq %r9, %r15, %r11
+# CHECK: encoding: [0x62,0x52,0x84,0x0c,0xf2,0xd9]
+ {nf} andnq %r9, %r15, %r11
+
+# CHECK: {evex} andnq %r9, %r15, %r11
+# CHECK: encoding: [0x62,0x52,0x84,0x08,0xf2,0xd9]
+ {evex} andnq %r9, %r15, %r11
+
+# CHECK: {nf} andnl 123(%rax,%rbx,4), %ecx, %edx
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {nf} andnl 123(%rax,%rbx,4), %ecx, %edx
+
+# CHECK: {evex} andnl 123(%rax,%rbx,4), %ecx, %edx
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {evex} andnl 123(%rax,%rbx,4), %ecx, %edx
+
+# CHECK: {nf} andnq 123(%rax,%rbx,4), %r9, %r15
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {nf} andnq 123(%rax,%rbx,4), %r9, %r15
+
+# CHECK: {evex} andnq 123(%rax,%rbx,4), %r9, %r15
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {evex} andnq 123(%rax,%rbx,4), %r9, %r15
+
# CHECK: andnl %r18d, %r22d, %r26d
# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2]
andnl %r18d, %r22d, %r26d
diff --git a/llvm/test/MC/X86/apx/andn-intel.s b/llvm/test/MC/X86/apx/andn-intel.s
index 583e6e763b1eca..4a369a0d3b6896 100644
--- a/llvm/test/MC/X86/apx/andn-intel.s
+++ b/llvm/test/MC/X86/apx/andn-intel.s
@@ -1,5 +1,37 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+# CHECK: {nf} andn r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x6c,0x0c,0xf2,0xd1]
+ {nf} andn r10d, edx, ecx
+
+# CHECK: {evex} andn r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x6c,0x08,0xf2,0xd1]
+ {evex} andn r10d, edx, ecx
+
+# CHECK: {nf} andn r11, r15, r9
+# CHECK: encoding: [0x62,0x52,0x84,0x0c,0xf2,0xd9]
+ {nf} andn r11, r15, r9
+
+# CHECK: {evex} andn r11, r15, r9
+# CHECK: encoding: [0x62,0x52,0x84,0x08,0xf2,0xd9]
+ {evex} andn r11, r15, r9
+
+# CHECK: {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {nf} andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+
+# CHECK: {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf2,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {evex} andn edx, ecx, dword ptr [rax + 4*rbx + 123]
+
+# CHECK: {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {nf} andn r15, r9, qword ptr [rax + 4*rbx + 123]
+
+# CHECK: {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123]
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf2,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {evex} andn r15, r9, qword ptr [rax + 4*rbx + 123]
+
# CHECK: andn r26d, r22d, r18d
# CHECK: encoding: [0x62,0x6a,0x4c,0x00,0xf2,0xd2]
andn r26d, r22d, r18d
diff --git a/llvm/test/MC/X86/apx/bextr-att.s b/llvm/test/MC/X86/apx/bextr-att.s
index 6095ffa389a34c..57f5d3e1c2b441 100644
--- a/llvm/test/MC/X86/apx/bextr-att.s
+++ b/llvm/test/MC/X86/apx/bextr-att.s
@@ -1,8 +1,40 @@
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-# ERROR-COUNT-4: error:
+# ERROR-COUNT-12: error:
# ERROR-NOT: error:
+# CHECK: {nf} bextrl %ecx, %edx, %r10d
+# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2]
+ {nf} bextrl %ecx, %edx, %r10d
+
+# CHECK: {evex} bextrl %ecx, %edx, %r10d
+# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2]
+ {evex} bextrl %ecx, %edx, %r10d
+
+# CHECK: {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {nf} bextrl %ecx, 123(%rax,%rbx,4), %edx
+
+# CHECK: {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {evex} bextrl %ecx, 123(%rax,%rbx,4), %edx
+
+# CHECK: {nf} bextrq %r9, %r15, %r11
+# CHECK: encoding: [0x62,0x52,0xb4,0x0c,0xf7,0xdf]
+ {nf} bextrq %r9, %r15, %r11
+
+# CHECK: {evex} bextrq %r9, %r15, %r11
+# CHECK: encoding: [0x62,0x52,0xb4,0x08,0xf7,0xdf]
+ {evex} bextrq %r9, %r15, %r11
+
+# CHECK: {nf} bextrq %r9, 123(%rax,%rbx,4), %r15
+# CHECK: encoding: [0x62,0x72,0xb4,0x0c,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {nf} bextrq %r9, 123(%rax,%rbx,4), %r15
+
+# CHECK: {evex} bextrq %r9, 123(%rax,%rbx,4), %r15
+# CHECK: encoding: [0x62,0x72,0xb4,0x08,0xf7,0xbc,0x98,0x7b,0x00,0x00,0x00]
+ {evex} bextrq %r9, 123(%rax,%rbx,4), %r15
+
# CHECK: bextrl %r18d, %r22d, %r26d
# CHECK: encoding: [0x62,0x6a,0x6c,0x00,0xf7,0xd6]
bextrl %r18d, %r22d, %r26d
diff --git a/llvm/test/MC/X86/apx/bextr-intel.s b/llvm/test/MC/X86/apx/bextr-intel.s
index af70c00c1d631d..7a133d6e50f34a 100644
--- a/llvm/test/MC/X86/apx/bextr-intel.s
+++ b/llvm/test/MC/X86/apx/bextr-intel.s
@@ -1,5 +1,37 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+# CHECK: {nf} bextr r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x74,0x0c,0xf7,0xd2]
+ {nf} bextr r10d, edx, ecx
+
+# CHECK: {evex} bextr r10d, edx, ecx
+# CHECK: encoding: [0x62,0x72,0x74,0x08,0xf7,0xd2]
+ {evex} bextr r10d, edx, ecx
+
+# CHECK: {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+# CHECK: encoding: [0x62,0xf2,0x74,0x0c,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {nf} bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+
+# CHECK: {evex} bextr edx, dword ptr [rax + 4*rbx + 123], ecx
+# CHECK: encoding: [0x62,0xf2,0x74,0x08,0xf7,0x94,0x98,0x7b,0x00,0x00,0x00]
+ {evex} bextr edx, dword ptr [ra...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/76709
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