[llvm] [AMDGPU][MC] Support src modifiers for v_mov_b32 and v_movrel* instructions (PR #76498)

[Joe Nash via llvm-commits]

https://github.com/Sisyph requested changes to this pull request.

Thanks for working on the issue. From the commit title it seems like you intended this to be MC layer only, but it looks like you have updated the patterns for mov with dpp such that they could select non-zero modifier operands. In that case we need support  in GCNDPPCombine for non-zero modifiers. There should be tests for combining all forms of MOV with dpp with an ALU, where the MOV has non-zero modifiers set. In GCNDPPCombine, at minimum we should abort forming an ALU with DPP if the mov has non-zero modifiers. And you can potentially do more, which would be to form DPP ALUs if a compatible set of non-zero modifiers is present on the MOV and the ALU.

https://github.com/llvm/llvm-project/pull/76498