[llvm] [AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (PR #75825)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 2 05:23:38 PST 2024
================
@@ -419,6 +427,33 @@ void AMDGPUPostLegalizerCombinerImpl::applyCombineSignExtendInReg(
MI.eraseFromParent();
}
+bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
+ MachineInstr &MI, unsigned &NewOpcode) const {
+ Register Src0 = MI.getOperand(1).getReg();
+ Register Src1 = MI.getOperand(2).getReg();
+ KnownBits Op0KnownBits = KB->getKnownBits(Src0);
+ unsigned Op0LeadingZeros = Op0KnownBits.countMinLeadingZeros();
+ KnownBits Op1KnownBits = KB->getKnownBits(Src1);
+ unsigned Op1LeadingZeros = Op1KnownBits.countMinLeadingZeros();
+ if (Op0LeadingZeros >= 32 && Op1LeadingZeros >= 32) {
+ NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32_PSEUDO;
+ return true;
+ }
+
+ unsigned Op0SignBits = KB->computeNumSignBits(Src0);
+ unsigned Op1SignBits = KB->computeNumSignBits(Src1);
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jayfoad wrote:
Done.
https://github.com/llvm/llvm-project/pull/75825
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