[llvm] [AMDGPU] Add CodeGen support for GFX12 s_mul_u64 (PR #75825)

[Jay Foad via llvm-commits]

================
@@ -419,6 +427,33 @@ void AMDGPUPostLegalizerCombinerImpl::applyCombineSignExtendInReg(
   MI.eraseFromParent();
 }
 
+bool AMDGPUPostLegalizerCombinerImpl::matchCombine_s_mul_u64(
+    MachineInstr &MI, unsigned &NewOpcode) const {
+  Register Src0 = MI.getOperand(1).getReg();
+  Register Src1 = MI.getOperand(2).getReg();
+  KnownBits Op0KnownBits = KB->getKnownBits(Src0);
+  unsigned Op0LeadingZeros = Op0KnownBits.countMinLeadingZeros();
+  KnownBits Op1KnownBits = KB->getKnownBits(Src1);
+  unsigned Op1LeadingZeros = Op1KnownBits.countMinLeadingZeros();
+  if (Op0LeadingZeros >= 32 && Op1LeadingZeros >= 32) {
+    NewOpcode = AMDGPU::G_AMDGPU_S_MUL_U64_U32_PSEUDO;
+    return true;
+  }
+
+  unsigned Op0SignBits = KB->computeNumSignBits(Src0);
+  unsigned Op1SignBits = KB->computeNumSignBits(Src1);
----------------
jayfoad wrote:

Done.

https://github.com/llvm/llvm-project/pull/75825