[llvm] [RISCV] Fix missing scaling by LMUL in cost model (PR #73342)

[Luke Lau via llvm-commits]

================
@@ -1154,7 +1157,7 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
     auto LT = getTypeLegalizationCost(RetTy);
     unsigned VPISD = getISDForVPIntrinsicID(ICA.getID());
     if (TLI->isOperationCustom(VPISD, LT.second))
-      return Cost * LT.first;
+      return Cost * LT.first * TLI->getLMULCost(LT.second);
----------------
lukel97 wrote:

Looks like only 5 of the 7 costed instructions are vector instructions here, we should ignore LMUL for those FRM swaps:

```llvm
declare <vscale x 2 x float>  @llvm.vp.roundtozero.nxv2f32 (<vscale x 2 x float>, <vscale x 2 x i1>, i32)

define <vscale x 2 x float> @f(<vscale x 2 x float> %x, <vscale x 2 x i1> %mask, i32 %avl) {
  %1 = call <vscale x 2 x float> @llvm.vp.roundtozero.nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x i1> %mask, i32 %avl)
  ret <vscale x 2 x float> %1
}
```

```asm
f:                                      # @f
	.cfi_startproc
# %bb.0:
	slli	a0, a0, 32
	srli	a0, a0, 32
	vsetvli	zero, a0, e32, m1, ta, ma
	vfabs.v	v9, v8, v0.t # costed
	lui	a0, 307200
	fmv.w.x	fa5, a0
	vsetvli	zero, zero, e32, m1, ta, mu
	vmflt.vf	v0, v9, fa5, v0.t # costed
	vsetvli	zero, zero, e32, m1, ta, ma
	fsrmi	a0, 1 # costed, but LMUL independent
	vfcvt.x.f.v	v9, v8, v0.t # costed
	fsrm	a0 # costed, but LMUL independent
	vfcvt.f.x.v	v9, v9, v0.t # costed
	vsetvli	zero, zero, e32, m1, ta, mu
	vfsgnj.vv	v8, v9, v8, v0.t # costed
	ret
```

https://github.com/llvm/llvm-project/pull/73342