[llvm] d8db273 - [X86][MC] Support Enc/Dec for EGPR for promoted CRC32 (#76434)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 1 18:48:47 PST 2024
Author: XinWang10
Date: 2024-01-02T10:48:42+08:00
New Revision: d8db2733c87ef2ee54c322cbee76711147a94948
URL: https://github.com/llvm/llvm-project/commit/d8db2733c87ef2ee54c322cbee76711147a94948
DIFF: https://github.com/llvm/llvm-project/commit/d8db2733c87ef2ee54c322cbee76711147a94948.diff
LOG: [X86][MC] Support Enc/Dec for EGPR for promoted CRC32 (#76434)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted CRC32 instruction
in EVEX space.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Added:
llvm/test/MC/Disassembler/X86/apx/crc32.txt
llvm/test/MC/X86/apx/crc32-att.s
llvm/test/MC/X86/apx/crc32-intel.s
Modified:
llvm/lib/Target/X86/X86InstrSSE.td
llvm/test/MC/X86/x86_64-asm-match.s
llvm/test/TableGen/x86-fold-tables.inc
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 357b1f30db5040..e8a1a2b83886f8 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6663,18 +6663,18 @@ let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
class Crc32r<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
: ITy<0xF1, MRMSrcReg, t, (outs rc:$dst), (ins rc:$src1, t.RegClass:$src2),
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, t.RegClass:$src2))]>,
- Sched<[WriteCRC32]> {
+ Sched<[WriteCRC32]>, NoCD8 {
let Constraints = "$src1 = $dst";
}
class Crc32m<X86TypeInfo t, RegisterClass rc, SDPatternOperator node>
: ITy<0xF1, MRMSrcMem, t, (outs rc:$dst), (ins rc:$src1, t.MemOperand:$src2),
"crc32", binop_args, [(set rc:$dst, (node rc:$src1, (load addr:$src2)))]>,
- Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]> {
+ Sched<[WriteCRC32.Folded, WriteCRC32.ReadAfterFold]>, NoCD8 {
let Constraints = "$src1 = $dst";
}
-let Predicates = [HasCRC32], OpMap = T8, OpPrefix = XD in {
+let Predicates = [HasCRC32, NoEGPR], OpMap = T8, OpPrefix = XD in {
def CRC32r32r8 : Crc32r<Xi8, GR32, int_x86_sse42_crc32_32_8>;
def CRC32r32m8 : Crc32m<Xi8, GR32, int_x86_sse42_crc32_32_8>;
def CRC32r32r16 : Crc32r<Xi16, GR32, int_x86_sse42_crc32_32_16>, OpSize16;
@@ -6688,6 +6688,20 @@ let Predicates = [HasCRC32], OpMap = T8, OpPrefix = XD in {
def CRC32r64m8 : Crc32m<Xi8, GR64, null_frag>, REX_W;
}
+let Predicates = [HasCRC32, HasEGPR, In64BitMode], OpMap = T_MAP4, OpEnc = EncEVEX in {
+ def CRC32r32r8_EVEX : Crc32r<Xi8, GR32, int_x86_sse42_crc32_32_8>;
+ def CRC32r32m8_EVEX : Crc32m<Xi8, GR32, int_x86_sse42_crc32_32_8>;
+ def CRC32r32r16_EVEX : Crc32r<Xi16, GR32, int_x86_sse42_crc32_32_16>, PD;
+ def CRC32r32m16_EVEX : Crc32m<Xi16, GR32, int_x86_sse42_crc32_32_16>, PD;
+ def CRC32r32r32_EVEX : Crc32r<Xi32, GR32, int_x86_sse42_crc32_32_32>;
+ def CRC32r32m32_EVEX : Crc32m<Xi32, GR32, int_x86_sse42_crc32_32_32>;
+ def CRC32r64r64_EVEX : Crc32r<Xi64, GR64, int_x86_sse42_crc32_64_64>;
+ def CRC32r64m64_EVEX : Crc32m<Xi64, GR64, int_x86_sse42_crc32_64_64>;
+ def CRC32r64r8_EVEX : Crc32r<Xi8, GR64, null_frag>, REX_W;
+ let mayLoad = 1 in
+ def CRC32r64m8_EVEX : Crc32m<Xi8, GR64, null_frag>, REX_W;
+}
+
//===----------------------------------------------------------------------===//
// SHA-NI Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/X86/apx/crc32.txt b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
new file mode 100644
index 00000000000000..0144f576b8ba77
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
@@ -0,0 +1,90 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: crc32b %al, %ebx
+# INTEL: crc32 ebx, al
+0x62,0xf4,0x7c,0x08,0xf0,0xd8
+
+# ATT: crc32b %al, %rbx
+# INTEL: crc32 rbx, al
+0x62,0xf4,0xfc,0x08,0xf0,0xd8
+
+# ATT: crc32w %ax, %ebx
+# INTEL: crc32 ebx, ax
+0x62,0xf4,0x7d,0x08,0xf1,0xd8
+
+# ATT: crc32l %eax, %ebx
+# INTEL: crc32 ebx, eax
+0x62,0xf4,0x7c,0x08,0xf1,0xd8
+
+# ATT: crc32q %rax, %rbx
+# INTEL: crc32 rbx, rax
+0x62,0xf4,0xfc,0x08,0xf1,0xd8
+
+# ATT: crc32w 291(%rax,%rbx,4), %ecx
+# INTEL: crc32 ecx, word ptr [rax + 4*rbx + 291]
+0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%rax,%rbx,4), %ecx
+# INTEL: crc32 ecx, dword ptr [rax + 4*rbx + 291]
+0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%rax,%rbx,4), %rcx
+# INTEL: crc32 rcx, byte ptr [rax + 4*rbx + 291]
+0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%rax,%rbx,4), %rcx
+# INTEL: crc32 rcx, qword ptr [rax + 4*rbx + 291]
+0x62,0xf4,0xfc,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
+
+# ATT: crc32b %r16b, %r22d
+# INTEL: crc32 r22d, r16b
+0x62,0xec,0x7c,0x08,0xf0,0xf0
+
+# ATT: crc32b %r16b, %r23
+# INTEL: crc32 r23, r16b
+0x62,0xec,0xfc,0x08,0xf0,0xf8
+
+# ATT: crc32w %r17w, %r22d
+# INTEL: crc32 r22d, r17w
+0x62,0xec,0x7d,0x08,0xf1,0xf1
+
+# ATT: crc32l %r18d, %r22d
+# INTEL: crc32 r22d, r18d
+0x62,0xec,0x7c,0x08,0xf1,0xf2
+
+# ATT: crc32q %r19, %r23
+# INTEL: crc32 r23, r19
+0x62,0xec,0xfc,0x08,0xf1,0xfb
+
+# ATT: crc32w 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32w 123(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b
+
+# ATT: crc32l 123(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b
+
+# ATT: crc32b 123(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b
+
+# ATT: crc32q 123(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0xf8,0x08,0xf1,0x5c,0xac,0x7b
diff --git a/llvm/test/MC/X86/apx/crc32-att.s b/llvm/test/MC/X86/apx/crc32-att.s
new file mode 100644
index 00000000000000..16f1f052dbf910
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-att.s
@@ -0,0 +1,92 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
+
+# ERROR-COUNT-22: error:
+# ERROR-NOT: error:
+# CHECK: {evex} crc32b %al, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xd8]
+ {evex} crc32b %al, %ebx
+
+# CHECK: {evex} crc32b %al, %rbx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0xd8]
+ {evex} crc32b %al, %rbx
+
+# CHECK: {evex} crc32w %ax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xd8]
+ {evex} crc32w %ax, %ebx
+
+# CHECK: {evex} crc32l %eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xd8]
+ {evex} crc32l %eax, %ebx
+
+# CHECK: {evex} crc32q %rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf1,0xd8]
+ {evex} crc32q %rax, %rbx
+
+# CHECK: {evex} crc32w 291(%rax,%rbx,4), %ecx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32w 291(%rax,%rbx,4), %ecx
+
+# CHECK: {evex} crc32l 291(%rax,%rbx,4), %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32l 291(%rax,%rbx,4), %ecx
+
+# CHECK: {evex} crc32b 291(%rax,%rbx,4), %rcx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32b 291(%rax,%rbx,4), %rcx
+
+# CHECK: {evex} crc32q 291(%rax,%rbx,4), %rcx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32q 291(%rax,%rbx,4), %rcx
+
+# CHECK: crc32b %r16b, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32b %r16b, %r22d
+
+# CHECK: crc32b %r16b, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32b %r16b, %r23
+
+# CHECK: crc32w %r17w, %r22d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32w %r17w, %r22d
+
+# CHECK: crc32l %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32l %r18d, %r22d
+
+# CHECK: crc32q %r19, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf1,0xfb]
+ crc32q %r19, %r23
+
+# CHECK: crc32w 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32w 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32l 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32b 291(%r28,%r29,4), %r19
+
+# CHECK: crc32q 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32q 291(%r28,%r29,4), %r19
+
+# CHECK: crc32w 123(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b]
+ crc32w 123(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 123(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b]
+ crc32l 123(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 123(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b]
+ crc32b 123(%r28,%r29,4), %r19
+
+# CHECK: crc32q 123(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf1,0x5c,0xac,0x7b]
+ crc32q 123(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/crc32-intel.s b/llvm/test/MC/X86/apx/crc32-intel.s
new file mode 100644
index 00000000000000..a7bc915a0a092e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-intel.s
@@ -0,0 +1,89 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: {evex} crc32 ebx, al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xd8]
+ {evex} crc32 ebx, al
+
+# CHECK: {evex} crc32 rbx, al
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0xd8]
+ {evex} crc32 rbx, al
+
+# CHECK: {evex} crc32 ebx, ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xd8]
+ {evex} crc32 ebx, ax
+
+# CHECK: {evex} crc32 ebx, eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xd8]
+ {evex} crc32 ebx, eax
+
+# CHECK: {evex} crc32 rbx, rax
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf1,0xd8]
+ {evex} crc32 rbx, rax
+
+# CHECK: {evex} crc32 ecx, word ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 ecx, word ptr [rax + 4*rbx + 291]
+
+# CHECK: {evex} crc32 ecx, dword ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 ecx, dword ptr [rax + 4*rbx + 291]
+
+# CHECK: {evex} crc32 rcx, byte ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 rcx, byte ptr [rax + 4*rbx + 291]
+
+# CHECK: {evex} crc32 rcx, qword ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 rcx, qword ptr [rax + 4*rbx + 291]
+
+# CHECK: crc32 r22d, r16b
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32 r22d, r16b
+
+# CHECK: crc32 r23, r16b
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32 r23, r16b
+
+# CHECK: crc32 r22d, r17w
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32 r22d, r17w
+
+# CHECK: crc32 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32 r22d, r18d
+
+# CHECK: crc32 r23, r19
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf1,0xfb]
+ crc32 r23, r19
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, word ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, byte ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, qword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b]
+ crc32 r18d, word ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b]
+ crc32 r19, byte ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf1,0x5c,0xac,0x7b]
+ crc32 r19, qword ptr [r28 + 4*r29 + 123]
diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index cb1a40d541537c..68d375ec3e4cd5 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -29,7 +29,7 @@
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 3 (Reg:xmm5): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
// CHECK: Opcode result: complete match, selecting this opcode
-// CHECK: AsmMatcher: found 2 encodings with mnemonic 'crc32l'
+// CHECK: AsmMatcher: found 4 encodings with mnemonic 'crc32l'
// CHECK: Trying to match opcode CRC32r32r32
// CHECK: Matching formal operand class MCK_GR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rbx,IndexReg=rcx,Scale=8,Disp=2125315823,SegReg=gs): Opcode result: multiple operand mismatches, ignoring this opcode
// CHECK: Trying to match opcode CRC32r32m32
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 7f7146806e27f7..8ac46a5b669249 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -1602,10 +1602,15 @@ static const X86FoldTableEntry Table2[] = {
{X86::CMPSSrr, X86::CMPSSrm, 0},
{X86::CMPSSrr_Int, X86::CMPSSrm_Int, TB_NO_REVERSE},
{X86::CRC32r32r16, X86::CRC32r32m16, 0},
+ {X86::CRC32r32r16_EVEX, X86::CRC32r32m16_EVEX, 0},
{X86::CRC32r32r32, X86::CRC32r32m32, 0},
+ {X86::CRC32r32r32_EVEX, X86::CRC32r32m32_EVEX, 0},
{X86::CRC32r32r8, X86::CRC32r32m8, 0},
+ {X86::CRC32r32r8_EVEX, X86::CRC32r32m8_EVEX, 0},
{X86::CRC32r64r64, X86::CRC32r64m64, 0},
+ {X86::CRC32r64r64_EVEX, X86::CRC32r64m64_EVEX, 0},
{X86::CRC32r64r8, X86::CRC32r64m8, 0},
+ {X86::CRC32r64r8_EVEX, X86::CRC32r64m8_EVEX, 0},
{X86::CVTSD2SSrr_Int, X86::CVTSD2SSrm_Int, TB_NO_REVERSE},
{X86::CVTSI2SDrr_Int, X86::CVTSI2SDrm_Int, 0},
{X86::CVTSI2SSrr_Int, X86::CVTSI2SSrm_Int, 0},
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