[llvm] e99752d - [MC,test] Improve RISCV/fixups-expr.s

[Fangrui Song via llvm-commits]

Author: Fangrui Song
Date: 2024-01-01T06:17:54-08:00
New Revision: e99752d8065477b7a471cace580f8e818eda7fb1

URL: https://github.com/llvm/llvm-project/commit/e99752d8065477b7a471cace580f8e818eda7fb1
DIFF: https://github.com/llvm/llvm-project/commit/e99752d8065477b7a471cace580f8e818eda7fb1.diff

LOG: [MC,test] Improve RISCV/fixups-expr.s

Added: 
    

Modified: 
    llvm/test/MC/RISCV/fixups-expr.s

Removed: 
    


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diff  --git a/llvm/test/MC/RISCV/fixups-expr.s b/llvm/test/MC/RISCV/fixups-expr.s
index 20e5aacac61928..8a02d29de1ab5e 100644
--- a/llvm/test/MC/RISCV/fixups-expr.s
+++ b/llvm/test/MC/RISCV/fixups-expr.s
@@ -31,19 +31,21 @@ G2:
 .half G2-G1
 .byte .L2-.L1
 .byte G2-G1
-# RELAX: 0x0 R_RISCV_ADD64 .L2 0x0
-# RELAX: 0x0 R_RISCV_SUB64 .L1 0x0
-# RELAX: 0x8 R_RISCV_ADD64 G2 0x0
-# RELAX: 0x8 R_RISCV_SUB64 G1 0x0
-# RELAX: 0x10 R_RISCV_ADD32 .L2 0x0
-# RELAX: 0x10 R_RISCV_SUB32 .L1 0x0
-# RELAX: 0x14 R_RISCV_ADD32 G2 0x0
-# RELAX: 0x14 R_RISCV_SUB32 G1 0x0
-# RELAX: 0x18 R_RISCV_ADD16 .L2 0x0
-# RELAX: 0x18 R_RISCV_SUB16 .L1 0x0
-# RELAX: 0x1A R_RISCV_ADD16 G2 0x0
-# RELAX: 0x1A R_RISCV_SUB16 G1 0x0
-# RELAX: 0x1C R_RISCV_ADD8 .L2 0x0
-# RELAX: 0x1C R_RISCV_SUB8 .L1 0x0
-# RELAX: 0x1D R_RISCV_ADD8 G2 0x0
-# RELAX: 0x1D R_RISCV_SUB8 G1 0x0
+# RELAX:      .rela.data {
+# RELAX-NEXT:   0x0 R_RISCV_ADD64 .L2 0x0
+# RELAX-NEXT:   0x0 R_RISCV_SUB64 .L1 0x0
+# RELAX-NEXT:   0x8 R_RISCV_ADD64 G2 0x0
+# RELAX-NEXT:   0x8 R_RISCV_SUB64 G1 0x0
+# RELAX-NEXT:   0x10 R_RISCV_ADD32 .L2 0x0
+# RELAX-NEXT:   0x10 R_RISCV_SUB32 .L1 0x0
+# RELAX-NEXT:   0x14 R_RISCV_ADD32 G2 0x0
+# RELAX-NEXT:   0x14 R_RISCV_SUB32 G1 0x0
+# RELAX-NEXT:   0x18 R_RISCV_ADD16 .L2 0x0
+# RELAX-NEXT:   0x18 R_RISCV_SUB16 .L1 0x0
+# RELAX-NEXT:   0x1A R_RISCV_ADD16 G2 0x0
+# RELAX-NEXT:   0x1A R_RISCV_SUB16 G1 0x0
+# RELAX-NEXT:   0x1C R_RISCV_ADD8 .L2 0x0
+# RELAX-NEXT:   0x1C R_RISCV_SUB8 .L1 0x0
+# RELAX-NEXT:   0x1D R_RISCV_ADD8 G2 0x0
+# RELAX-NEXT:   0x1D R_RISCV_SUB8 G1 0x0
+# RELAX-NEXT: }