[llvm] [FastISel][AArch64] Compare Instruction Miscompilation Fix (PR #75993)

[via llvm-commits]

================
@@ -1233,7 +1233,11 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
       isValueAvailable(RHS)) {
     if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
       if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
-        if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
+        if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4) &&
+            !NeedExtend) {
+          // We can only fold instructions that doesn't need extension because
----------------
brendaso1 wrote:

Ah Gotcha. You're right, if `ExtendType != AArch64_AM::InvalidShiftExtend`, NeedExtend is always true. So the logic would never be reached. Maybe it's a better idea to remove that part of the logic all together? 

https://github.com/llvm/llvm-project/pull/75993