[llvm] Missing AArch64ISD::BICi handling (PR #76644)

[Simon Pilgrim via llvm-commits]

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@@ -26658,6 +26670,18 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
     // used - simplify to just Val.
     return TLO.CombineTo(Op, ShiftR->getOperand(0));
   }
+  case AArch64ISD::BICi: {
+    // Fold BICi if all destination bits already known to be zeroed
+    SDValue Op0 = Op.getOperand(0);
+    KnownBits KnownOp0 = TLO.DAG.computeKnownBits(Op0, 0);
+    APInt Shift = Op.getConstantOperandAPInt(2);
+    APInt Op1Val = Op.getConstantOperandAPInt(1);
+    APInt BitsToClear = Op1Val.shl(Shift).zextOrTrunc(KnownOp0.getBitWidth());
+    APInt AlreadyZeroedBitsToClear = BitsToClear & KnownOp0.Zero;
+    if (AlreadyZeroedBitsToClear == BitsToClear)
+      return TLO.CombineTo(Op, Op0);
+    return false;
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RKSimon wrote:

Return the calculated KnownBits (copy the AArch64TargetLowering::computeKnownBitsForTargetNode implementation).

https://github.com/llvm/llvm-project/pull/76644