[llvm] Missing AArch64ISD::BICi handling (PR #76644)

[Simon Pilgrim via llvm-commits]

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@@ -23672,6 +23672,18 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
     if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false))
       return R;
     return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
+  case AArch64ISD::BICi: {
+    KnownBits Known;
+    APInt DemandedElts(32, N->getValueType(0).getVectorNumElements());
+    APInt EltSize(32, N->getValueType(0).getScalarSizeInBits());
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RKSimon wrote:

Why is this hardcoded to 32?

https://github.com/llvm/llvm-project/pull/76644