[llvm] [X86][BF16] Add subvec_zero_lowering patterns (PR #76507)

[Simon Pilgrim via llvm-commits]

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@@ -3743,7 +3743,7 @@ static SDValue getZeroVector(MVT VT, const X86Subtarget &Subtarget,
   SDValue Vec;
   if (!Subtarget.hasSSE2() && VT.is128BitVector()) {
     Vec = DAG.getConstantFP(+0.0, dl, MVT::v4f32);
-  } else if (VT.isFloatingPoint()) {
+  } else if (VT.isFloatingPoint() && VT.getVectorElementType() != MVT::bf16) {
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RKSimon wrote:

Could we test for isTypeLegal(VT.getVectorElementType()) instead?

https://github.com/llvm/llvm-project/pull/76507