[llvm] f9d161f - [M68k][NFC] Rename MximmSExt8/16/32 to Mxi8/16/32immSExt8/16/32
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 29 11:54:24 PST 2023
Author: Min-Yih Hsu
Date: 2023-12-29T11:52:49-08:00
New Revision: f9d161f0b2bf2b9a69184751b23642eb8b2c70de
URL: https://github.com/llvm/llvm-project/commit/f9d161f0b2bf2b9a69184751b23642eb8b2c70de
DIFF: https://github.com/llvm/llvm-project/commit/f9d161f0b2bf2b9a69184751b23642eb8b2c70de.diff
LOG: [M68k][NFC] Rename MximmSExt8/16/32 to Mxi8/16/32immSExt8/16/32
The MximmSExt8/16/32 should be "any immediate that can be represented by
8/16/32-bit signed integer", hence it shouldn't express an explicit
type. Rename those into Mxi8/16/32immSExt8/16/32.
NFC.
Added:
Modified:
llvm/lib/Target/M68k/M68kInstrArithmetic.td
llvm/lib/Target/M68k/M68kInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/M68k/M68kInstrArithmetic.td b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
index 1f5f1e815e2bff..3532e56e741705 100644
--- a/llvm/lib/Target/M68k/M68kInstrArithmetic.td
+++ b/llvm/lib/Target/M68k/M68kInstrArithmetic.td
@@ -685,43 +685,43 @@ def : Pat<(urem i16:$dst, i16:$opd),
MxSubRegIndex16Lo)>;
// RI i8
-def : Pat<(sdiv i8:$dst, MximmSExt8:$opd),
+def : Pat<(sdiv i8:$dst, Mxi8immSExt8:$opd),
(EXTRACT_SUBREG
(SDIVd32i16 (MOVSXd32d8 $dst), (as_i16imm $opd)),
MxSubRegIndex8Lo)>;
-def : Pat<(udiv i8:$dst, MximmSExt8:$opd),
+def : Pat<(udiv i8:$dst, Mxi8immSExt8:$opd),
(EXTRACT_SUBREG
(UDIVd32i16 (MOVZXd32d8 $dst), (as_i16imm $opd)),
MxSubRegIndex8Lo)>;
-def : Pat<(srem i8:$dst, MximmSExt8:$opd),
+def : Pat<(srem i8:$dst, Mxi8immSExt8:$opd),
(EXTRACT_SUBREG
(ASR32di (ASR32di (SDIVd32i16 (MOVSXd32d8 $dst), (as_i16imm $opd)), 8), 8),
MxSubRegIndex8Lo)>;
-def : Pat<(urem i8:$dst, MximmSExt8:$opd),
+def : Pat<(urem i8:$dst, Mxi8immSExt8:$opd),
(EXTRACT_SUBREG
(LSR32di (LSR32di (UDIVd32i16 (MOVZXd32d8 $dst), (as_i16imm $opd)), 8), 8),
MxSubRegIndex8Lo)>;
// RI i16
-def : Pat<(sdiv i16:$dst, MximmSExt16:$opd),
+def : Pat<(sdiv i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(SDIVd32i16 (MOVSXd32d16 $dst), imm:$opd),
MxSubRegIndex16Lo)>;
-def : Pat<(udiv i16:$dst, MximmSExt16:$opd),
+def : Pat<(udiv i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(UDIVd32i16 (MOVZXd32d16 $dst), imm:$opd),
MxSubRegIndex16Lo)>;
-def : Pat<(srem i16:$dst, MximmSExt16:$opd),
+def : Pat<(srem i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(ASR32di (ASR32di (SDIVd32i16 (MOVSXd32d16 $dst), imm:$opd), 8), 8),
MxSubRegIndex16Lo)>;
-def : Pat<(urem i16:$dst, MximmSExt16:$opd),
+def : Pat<(urem i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(LSR32di (LSR32di (UDIVd32i16 (MOVZXd32d16 $dst), imm:$opd), 8), 8),
MxSubRegIndex16Lo)>;
@@ -752,17 +752,17 @@ def : Pat<(mul i32:$dst, i32:$opd), (SMULd32d32 $dst, $opd)>;
// RI
-def : Pat<(mul i16:$dst, MximmSExt16:$opd),
+def : Pat<(mul i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(SMULd32i16 (MOVXd32d16 $dst), imm:$opd),
MxSubRegIndex16Lo)>;
-def : Pat<(mulhs i16:$dst, MximmSExt16:$opd),
+def : Pat<(mulhs i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(ASR32di (ASR32di (SMULd32i16 (MOVXd32d16 $dst), imm:$opd), 8), 8),
MxSubRegIndex16Lo)>;
-def : Pat<(mulhu i16:$dst, MximmSExt16:$opd),
+def : Pat<(mulhu i16:$dst, Mxi16immSExt16:$opd),
(EXTRACT_SUBREG
(LSR32di (LSR32di (UMULd32i16 (MOVXd32d16 $dst), imm:$opd), 8), 8),
MxSubRegIndex16Lo)>;
@@ -873,16 +873,16 @@ foreach N = ["add", "addc"] in {
(ADD32df MxDRD32:$src, MxType32.FOp:$opd)>;
// add reg, imm
- def : Pat<(!cast<SDNode>(N) i8: $src, MximmSExt8:$opd),
+ def : Pat<(!cast<SDNode>(N) i8: $src, Mxi8immSExt8:$opd),
(ADD8di MxDRD8 :$src, imm:$opd)>;
- def : Pat<(!cast<SDNode>(N) i16:$src, MximmSExt16:$opd),
+ def : Pat<(!cast<SDNode>(N) i16:$src, Mxi16immSExt16:$opd),
(ADD16di MxDRD16:$src, imm:$opd)>;
// LEAp is more complex and thus will be selected over normal ADD32ri but it cannot
// be used with data registers, here by adding complexity to a simple ADD32ri insts
// we make sure it will be selected over LEAp
let AddedComplexity = 15 in {
- def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd),
+ def : Pat<(!cast<SDNode>(N) i32:$src, Mxi32immSExt32:$opd),
(ADD32di MxDRD32:$src, imm:$opd)>;
} // AddedComplexity = 15
@@ -941,11 +941,11 @@ foreach N = ["sub", "subc"] in {
(SUB32df MxDRD32:$src, MxType32.FOp:$opd)>;
// sub reg, imm
- def : Pat<(!cast<SDNode>(N) i8 :$src, MximmSExt8 :$opd),
+ def : Pat<(!cast<SDNode>(N) i8 :$src, Mxi8immSExt8 :$opd),
(SUB8di MxDRD8 :$src, imm:$opd)>;
- def : Pat<(!cast<SDNode>(N) i16:$src, MximmSExt16:$opd),
+ def : Pat<(!cast<SDNode>(N) i16:$src, Mxi16immSExt16:$opd),
(SUB16di MxDRD16:$src, imm:$opd)>;
- def : Pat<(!cast<SDNode>(N) i32:$src, MximmSExt32:$opd),
+ def : Pat<(!cast<SDNode>(N) i32:$src, Mxi32immSExt32:$opd),
(SUB32di MxDRD32:$src, imm:$opd)>;
// sub imm, (An)
@@ -974,11 +974,11 @@ multiclass BitwisePat<string INST, SDNode OP> {
def : Pat<(OP i32:$src, i32:$opd),
(!cast<MxInst>(INST#"32dd") MxDRD32:$src, MxDRD32:$opd)>;
// op reg, imm
- def : Pat<(OP i8: $src, MximmSExt8 :$opd),
+ def : Pat<(OP i8: $src, Mxi8immSExt8 :$opd),
(!cast<MxInst>(INST#"8di") MxDRD8 :$src, imm:$opd)>;
- def : Pat<(OP i16:$src, MximmSExt16:$opd),
+ def : Pat<(OP i16:$src, Mxi16immSExt16:$opd),
(!cast<MxInst>(INST#"16di") MxDRD16:$src, imm:$opd)>;
- def : Pat<(OP i32:$src, MximmSExt32:$opd),
+ def : Pat<(OP i32:$src, Mxi32immSExt32:$opd),
(!cast<MxInst>(INST#"32di") MxDRD32:$src, imm:$opd)>;
}
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 1e40c3c48990d4..84eb8e56da760b 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -513,9 +513,14 @@ def MxCP_PCI : ComplexPattern<iPTR, 2, "SelectPCI",
// Pattern Fragments
//===----------------------------------------------------------------------===//
-def MximmSExt8 : PatLeaf<(i8 imm)>;
-def MximmSExt16 : PatLeaf<(i16 imm)>;
-def MximmSExt32 : PatLeaf<(i32 imm)>;
+def Mxi8immSExt8 : PatLeaf<(i8 imm)>;
+def MximmSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
+
+def Mxi16immSExt16 : PatLeaf<(i16 imm)>;
+def MximmSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
+
+def Mxi32immSExt32 : PatLeaf<(i32 imm)>;
+def MximmSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>;
// Used for Shifts and Rotations, since M68k immediates in these instructions
// are 1 <= i <= 8. Generally, if immediate is bigger than 8 it will be moved
@@ -708,7 +713,7 @@ foreach size = [8, 16, 32] in {
// #imm
def MxOp#size#AddrMode_i
: MxImmOpBundle<size, !cast<MxOperand>("Mxi"#size#"imm"),
- !cast<PatFrag>("MximmSExt"#size)>;
+ !cast<PatFrag>("Mxi"#size#"immSExt"#size)>;
} // foreach size = [8, 16, 32]
foreach size = [16, 32] in {
@@ -738,7 +743,7 @@ class MxType8Class<string rLet, MxOperand reg>
MxAL8, MxCP_AL,
MxPCD8, MxCP_PCD,
MxPCI8, MxCP_PCI,
- Mxi8imm, MximmSExt8,
+ Mxi8imm, Mxi8immSExt8,
Mxloadi8>;
def MxType8 : MxType8Class<?,?>;
@@ -753,7 +758,7 @@ class MxType16Class<string rLet, MxOperand reg>
MxAL16, MxCP_AL,
MxPCD16, MxCP_PCD,
MxPCI16, MxCP_PCI,
- Mxi16imm, MximmSExt16,
+ Mxi16imm, Mxi16immSExt16,
Mxloadi16>;
def MxType16 : MxType16Class<?,?>;
@@ -768,7 +773,7 @@ class MxType32Class<string rLet, MxOperand reg>
MxAL32, MxCP_AL,
MxPCD32, MxCP_PCD,
MxPCI32, MxCP_PCI,
- Mxi32imm, MximmSExt32,
+ Mxi32imm, Mxi32immSExt32,
Mxloadi32>;
def MxType32 : MxType32Class<?,?>;
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