[llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)

Yingwei Zheng via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 28 22:36:48 PST 2023

Previous message: [llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)
Next message: [llvm] 47c88bc - [LoongArch] Fix LASX vector_extract codegen
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

https://github.com/dtcxzyw closed https://github.com/llvm/llvm-project/pull/72340

Previous message: [llvm] [RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension (PR #72340)
Next message: [llvm] 47c88bc - [LoongArch] Fix LASX vector_extract codegen
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list