[llvm] 1c87d5c - [AArch64][GlobalISel] Lower fminnm/fmaxnm through Global ISel
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 28 12:02:35 PST 2023
Author: David Green
Date: 2023-12-28T20:02:30Z
New Revision: 1c87d5c4fc55cdd67bc879d918480148e64016be
URL: https://github.com/llvm/llvm-project/commit/1c87d5c4fc55cdd67bc879d918480148e64016be
DIFF: https://github.com/llvm/llvm-project/commit/1c87d5c4fc55cdd67bc879d918480148e64016be.diff
LOG: [AArch64][GlobalISel] Lower fminnm/fmaxnm through Global ISel
Whilst this might technically not be correct if a combine treats signed zeroes
differently, where the neon operations are more defined than the minnum/maxnum
nodes. It mirrors what SDAG does, which allows us to lower aarch64_neon_fminnm
and aarch64_neon_fmaxnm through the existing selection patterns.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/arm64-vmax.ll
llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 8b909f53c84460..4eccaa5be3cf19 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1406,7 +1406,9 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
case Intrinsic::aarch64_neon_umax:
case Intrinsic::aarch64_neon_umin:
case Intrinsic::aarch64_neon_fmax:
- case Intrinsic::aarch64_neon_fmin: {
+ case Intrinsic::aarch64_neon_fmin:
+ case Intrinsic::aarch64_neon_fmaxnm:
+ case Intrinsic::aarch64_neon_fminnm: {
MachineIRBuilder MIB(MI);
if (IntrinsicID == Intrinsic::aarch64_neon_smax)
MIB.buildSMax(MI.getOperand(0), MI.getOperand(2), MI.getOperand(3));
@@ -1422,6 +1424,12 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
else if (IntrinsicID == Intrinsic::aarch64_neon_fmin)
MIB.buildInstr(TargetOpcode::G_FMINIMUM, {MI.getOperand(0)},
{MI.getOperand(2), MI.getOperand(3)});
+ else if (IntrinsicID == Intrinsic::aarch64_neon_fmaxnm)
+ MIB.buildInstr(TargetOpcode::G_FMAXNUM, {MI.getOperand(0)},
+ {MI.getOperand(2), MI.getOperand(3)});
+ else if (IntrinsicID == Intrinsic::aarch64_neon_fminnm)
+ MIB.buildInstr(TargetOpcode::G_FMINNUM, {MI.getOperand(0)},
+ {MI.getOperand(2), MI.getOperand(3)});
MI.eraseFromParent();
return true;
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vmax.ll b/llvm/test/CodeGen/AArch64/arm64-vmax.ll
index d0a36b76cc61a1..5a132a33c5da04 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vmax.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vmax.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -global-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: smax_8b:
diff --git a/llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll b/llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll
index b9cd1bec17745e..332fca23815c21 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vminmaxnm.ll
@@ -1,57 +1,75 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel | FileCheck %s
define <2 x float> @f1(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.2s v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm.2s v0, v0, v1
+; CHECK-NEXT: ret
%vmaxnm2.i = tail call <2 x float> @llvm.aarch64.neon.fmaxnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
ret <2 x float> %vmaxnm2.i
}
define <4 x float> @f2(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.4s v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm.4s v0, v0, v1
+; CHECK-NEXT: ret
%vmaxnm2.i = tail call <4 x float> @llvm.aarch64.neon.fmaxnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
ret <4 x float> %vmaxnm2.i
}
define <2 x double> @f3(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
-; CHECK: fmaxnm.2d v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f3:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm.2d v0, v0, v1
+; CHECK-NEXT: ret
%vmaxnm2.i = tail call <2 x double> @llvm.aarch64.neon.fmaxnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
ret <2 x double> %vmaxnm2.i
}
define <2 x float> @f4(<2 x float> %a, <2 x float> %b) nounwind readnone ssp {
-; CHECK: fminnm.2s v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f4:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm.2s v0, v0, v1
+; CHECK-NEXT: ret
%vminnm2.i = tail call <2 x float> @llvm.aarch64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b) nounwind
ret <2 x float> %vminnm2.i
}
define <4 x float> @f5(<4 x float> %a, <4 x float> %b) nounwind readnone ssp {
-; CHECK: fminnm.4s v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f5:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm.4s v0, v0, v1
+; CHECK-NEXT: ret
%vminnm2.i = tail call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b) nounwind
ret <4 x float> %vminnm2.i
}
define <2 x double> @f6(<2 x double> %a, <2 x double> %b) nounwind readnone ssp {
-; CHECK: fminnm.2d v0, v0, v1
-; CHECK: ret
+; CHECK-LABEL: f6:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm.2d v0, v0, v1
+; CHECK-NEXT: ret
%vminnm2.i = tail call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> %b) nounwind
ret <2 x double> %vminnm2.i
}
define float @f7(float %a, float %b) nounwind readnone ssp {
-; CHECK: fmaxnm s0, s0, s1
-; CHECK: ret
+; CHECK-LABEL: f7:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnm s0, s0, s1
+; CHECK-NEXT: ret
%vmaxnm2.i = tail call float @llvm.aarch64.neon.fmaxnm.f32(float %a, float %b) nounwind
ret float %vmaxnm2.i
}
define double @f8(double %a, double %b) nounwind readnone ssp {
-; CHECK: fminnm d0, d0, d1
-; CHECK: ret
+; CHECK-LABEL: f8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnm d0, d0, d1
+; CHECK-NEXT: ret
%vmaxnm2.i = tail call double @llvm.aarch64.neon.fminnm.f64(double %a, double %b) nounwind
ret double %vmaxnm2.i
}
@@ -67,14 +85,18 @@ declare double @llvm.aarch64.neon.fminnm.f64(double, double) nounwind readnone
define double @test_fmaxnmv(<2 x double> %in) {
; CHECK-LABEL: test_fmaxnmv:
-; CHECK: fmaxnmp.2d d0, v0
+; CHECK: // %bb.0:
+; CHECK-NEXT: fmaxnmp.2d d0, v0
+; CHECK-NEXT: ret
%max = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)
ret double %max
}
define double @test_fminnmv(<2 x double> %in) {
; CHECK-LABEL: test_fminnmv:
-; CHECK: fminnmp.2d d0, v0
+; CHECK: // %bb.0:
+; CHECK-NEXT: fminnmp.2d d0, v0
+; CHECK-NEXT: ret
%min = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)
ret double %min
}
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