[llvm] [PowerPC] Expand FSINCOS of fp128 (PR #76494)
Qiu Chaofan via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 28 00:58:43 PST 2023
https://github.com/ecnelises updated https://github.com/llvm/llvm-project/pull/76494
>From 740ac4f427a71fb6a91676bc944980229f9812ea Mon Sep 17 00:00:00 2001
From: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: Thu, 28 Dec 2023 16:13:50 +0800
Subject: [PATCH 1/2] [PowerPC] Expand FSINCOS of fp128
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +
llvm/test/CodeGen/PowerPC/f128-arith.ll | 60 +++++++++++++++++++++
2 files changed, 62 insertions(+)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ae0d3b76f89a36..385b3b74c34d65 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1176,6 +1176,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setTruncStoreAction(MVT::f128, MVT::f32, Expand);
// No implementation for these ops for PowerPC.
+ setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
setOperationAction(ISD::FSIN, MVT::f128, Expand);
setOperationAction(ISD::FCOS, MVT::f128, Expand);
setOperationAction(ISD::FPOW, MVT::f128, Expand);
@@ -1411,6 +1412,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setLibcallName(RTLIB::EXP2_F128, "exp2f128");
setLibcallName(RTLIB::SIN_F128, "sinf128");
setLibcallName(RTLIB::COS_F128, "cosf128");
+ setLibcallName(RTLIB::SINCOS_F128, "sincosf128");
setLibcallName(RTLIB::POW_F128, "powf128");
setLibcallName(RTLIB::FMIN_F128, "fminf128");
setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index 18c0f25ed10e84..a9323beaf1d78d 100644
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -419,6 +419,66 @@ entry:
}
declare fp128 @llvm.cos.f128(fp128 %Val)
+define fp128 @qp_sincos(ptr nocapture readonly %a) {
+; CHECK-LABEL: qp_sincos:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr r0
+; CHECK-NEXT: stdu r1, -64(r1)
+; CHECK-NEXT: std r0, 80(r1)
+; CHECK-NEXT: .cfi_def_cfa_offset 64
+; CHECK-NEXT: .cfi_offset lr, 16
+; CHECK-NEXT: lxv v2, 0(r3)
+; CHECK-NEXT: addi r5, r1, 48
+; CHECK-NEXT: addi r6, r1, 32
+; CHECK-NEXT: bl sincosf128
+; CHECK-NEXT: nop
+; CHECK-NEXT: lxv v2, 48(r1)
+; CHECK-NEXT: lxv v3, 32(r1)
+; CHECK-NEXT: xsmulqp v2, v3, v2
+; CHECK-NEXT: addi r1, r1, 64
+; CHECK-NEXT: ld r0, 16(r1)
+; CHECK-NEXT: mtlr r0
+; CHECK-NEXT: blr
+;
+; CHECK-P8-LABEL: qp_sincos:
+; CHECK-P8: # %bb.0: # %entry
+; CHECK-P8-NEXT: mflr r0
+; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
+; CHECK-P8-NEXT: .cfi_offset lr, 16
+; CHECK-P8-NEXT: .cfi_offset r29, -24
+; CHECK-P8-NEXT: .cfi_offset r30, -16
+; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT: stdu r1, -96(r1)
+; CHECK-P8-NEXT: std r0, 112(r1)
+; CHECK-P8-NEXT: addi r30, r1, 48
+; CHECK-P8-NEXT: addi r29, r1, 32
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT: mr r5, r30
+; CHECK-P8-NEXT: mr r6, r29
+; CHECK-P8-NEXT: xxswapd v2, vs0
+; CHECK-P8-NEXT: bl sincosf128
+; CHECK-P8-NEXT: nop
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r29
+; CHECK-P8-NEXT: xxswapd v2, vs0
+; CHECK-P8-NEXT: lxvd2x vs0, 0, r30
+; CHECK-P8-NEXT: xxswapd v3, vs0
+; CHECK-P8-NEXT: bl __mulkf3
+; CHECK-P8-NEXT: nop
+; CHECK-P8-NEXT: addi r1, r1, 96
+; CHECK-P8-NEXT: ld r0, 16(r1)
+; CHECK-P8-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT: mtlr r0
+; CHECK-P8-NEXT: blr
+entry:
+ %0 = load fp128, ptr %a, align 16
+ %1 = tail call fp128 @llvm.cos.f128(fp128 %0)
+ %2 = tail call fp128 @llvm.sin.f128(fp128 %0)
+ %3 = fmul fp128 %1, %2
+ ret fp128 %3
+}
+
define fp128 @qp_log(ptr nocapture readonly %a) {
; CHECK-LABEL: qp_log:
; CHECK: # %bb.0: # %entry
>From f473d622b41278bf2f0e61d453abef8c7eaf7509 Mon Sep 17 00:00:00 2001
From: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: Thu, 28 Dec 2023 16:58:24 +0800
Subject: [PATCH 2/2] Remove cfi offset mark
---
llvm/test/CodeGen/PowerPC/f128-arith.ll | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/PowerPC/f128-arith.ll b/llvm/test/CodeGen/PowerPC/f128-arith.ll
index a9323beaf1d78d..35e5d61947ead7 100644
--- a/llvm/test/CodeGen/PowerPC/f128-arith.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-arith.ll
@@ -419,17 +419,15 @@ entry:
}
declare fp128 @llvm.cos.f128(fp128 %Val)
-define fp128 @qp_sincos(ptr nocapture readonly %a) {
+define fp128 @qp_sincos(ptr nocapture readonly %a) nounwind {
; CHECK-LABEL: qp_sincos:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: std r0, 80(r1)
-; CHECK-NEXT: .cfi_def_cfa_offset 64
-; CHECK-NEXT: .cfi_offset lr, 16
-; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: addi r5, r1, 48
; CHECK-NEXT: addi r6, r1, 32
+; CHECK-NEXT: lxv v2, 0(r3)
; CHECK-NEXT: bl sincosf128
; CHECK-NEXT: nop
; CHECK-NEXT: lxv v2, 48(r1)
@@ -443,10 +441,6 @@ define fp128 @qp_sincos(ptr nocapture readonly %a) {
; CHECK-P8-LABEL: qp_sincos:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mflr r0
-; CHECK-P8-NEXT: .cfi_def_cfa_offset 96
-; CHECK-P8-NEXT: .cfi_offset lr, 16
-; CHECK-P8-NEXT: .cfi_offset r29, -24
-; CHECK-P8-NEXT: .cfi_offset r30, -16
; CHECK-P8-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; CHECK-P8-NEXT: stdu r1, -96(r1)
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