[llvm] [RISCV] Collect function features in AsmPrinter before emission (#76231) (PR #76437)

[Andreu Carminati via llvm-commits]

================
@@ -363,13 +370,23 @@ bool RISCVAsmPrinter::emitDirectiveOptionArch() {
   return false;
 }
 
+bool RISCVAsmPrinter::doInitialization(Module &M) {
+
+  CommonSTI->setFeatureBits(TM.getMCSubtargetInfo()->getFeatureBits());
+  return AsmPrinter::doInitialization(M);
+}
+
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget<RISCVSubtarget>();
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
 
   bool EmittedOptionArch = emitDirectiveOptionArch();
 
+  // Collect flags from this function.
+  CommonSTI->setFeatureBits(CommonSTI->getFeatureBits() |
----------------
andcarminati wrote:

> I don't think we can just union the features. Some features are incompatible, like F and Zfinx.

Hi @topperc, you have an interesting point. I tried a change in my test case, mixing incompatible feature flags, like:

```
attributes #0 = { nounwind "target-features"="+32bit,+d,+zicsr" }
attributes #1 = { nounwind "target-features"="+32bit,+d,+f,+m" }
attributes #2 = { nounwind "target-features"="+32bit,+f,+c" }
attributes #3 = { nounwind "target-features"="+32bit,+a,+zfinx" }
```
Without the PR, we generated the ` Value: rv32i2p1 ` in the elf, but with the PR, I got:

```
LLVM ERROR: 'f' and 'zfinx' extensions are incompatible

PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
Stack dump: [...]
```
Do you think it is a useful case to have mixed (and even incompatible) flags in the same module? I only can think about some multicore asymmetric environments...

https://github.com/llvm/llvm-project/pull/76437