[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted CRC32 (PR #76434)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 27 23:17:34 PST 2023
https://github.com/XinWang10 updated https://github.com/llvm/llvm-project/pull/76434
>From 74421860e635d3ffcce1d4c14adf4f285f3e2fad Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 27 Dec 2023 02:40:39 -0800
Subject: [PATCH 1/2] [X86][MC] Support Enc/Dec for EGPR for promoted CRC32
---
llvm/lib/Target/X86/X86InstrSSE.td | 24 +++++++
llvm/test/MC/Disassembler/X86/apx/crc32.txt | 74 +++++++++++++++++++++
llvm/test/MC/X86/apx/crc32-att.s | 73 ++++++++++++++++++++
llvm/test/MC/X86/apx/crc32-intel.s | 73 ++++++++++++++++++++
llvm/test/MC/X86/x86_64-asm-match.s | 2 +-
llvm/test/TableGen/x86-fold-tables.inc | 5 ++
6 files changed, 250 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/crc32.txt
create mode 100644 llvm/test/MC/X86/apx/crc32-att.s
create mode 100644 llvm/test/MC/X86/apx/crc32-intel.s
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index df1f0b5b4ca727..60555c13125fc1 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6698,6 +6698,30 @@ let Constraints = "$src1 = $dst" in {
def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
null_frag>, REX_W;
}
+
+ def CRC32r32m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
+ int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ def CRC32r32r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
+ int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ def CRC32r32m16_EVEX : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
+ int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ def CRC32r32r16_EVEX : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
+ int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ def CRC32r32m32_EVEX : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
+ int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ def CRC32r32r32_EVEX : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
+ int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ def CRC32r64m64_EVEX : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ def CRC32r64r64_EVEX : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ let hasSideEffects = 0 in {
+ let mayLoad = 1 in
+ def CRC32r64m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
+ null_frag>, REX_W, EVEX, T_MAP4, PS;
+ def CRC32r64r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
+ null_frag>, REX_W, EVEX, T_MAP4, PS;
+ }
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/X86/apx/crc32.txt b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
new file mode 100644
index 00000000000000..954fdbcdedcbd4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
@@ -0,0 +1,74 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: crc32b %r16b, %r22d
+# INTEL: crc32 r22d, r16b
+0x62,0xec,0x7c,0x08,0xf0,0xf0
+
+# ATT: crc32b %r16b, %r23
+# INTEL: crc32 r23, r16b
+0x62,0xec,0xfc,0x08,0xf0,0xf8
+
+# ATT: crc32w %r17w, %r22d
+# INTEL: crc32 r22d, r17w
+0x62,0xec,0x7d,0x08,0xf1,0xf1
+
+# ATT: crc32l %r18d, %r22d
+# INTEL: crc32 r22d, r18d
+0x62,0xec,0x7c,0x08,0xf1,0xf2
+
+# ATT: crc32q %r19, %r23
+# INTEL: crc32 r23, r19
+0x62,0xec,0xfd,0x08,0xf1,0xfb
+
+# ATT: crc32w 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b %r16b, %r22d
+# INTEL: crc32 r22d, r16b
+0x62,0xec,0x7c,0x08,0xf0,0xf0
+
+# ATT: crc32b %r16b, %r23
+# INTEL: crc32 r23, r16b
+0x62,0xec,0xfc,0x08,0xf0,0xf8
+
+# ATT: crc32w %r17w, %r22d
+# INTEL: crc32 r22d, r17w
+0x62,0xec,0x7d,0x08,0xf1,0xf1
+
+# ATT: crc32l %r18d, %r22d
+# INTEL: crc32 r22d, r18d
+0x62,0xec,0x7c,0x08,0xf1,0xf2
+
+# ATT: crc32q %r19, %r23
+# INTEL: crc32 r23, r19
+0x62,0xec,0xfd,0x08,0xf1,0xfb
+
+# ATT: crc32w 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/crc32-att.s b/llvm/test/MC/X86/apx/crc32-att.s
new file mode 100644
index 00000000000000..5477f913e24e22
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-att.s
@@ -0,0 +1,73 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: crc32b %r16b, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32b %r16b, %r22d
+
+# CHECK: crc32b %r16b, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32b %r16b, %r23
+
+# CHECK: crc32w %r17w, %r22d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32w %r17w, %r22d
+
+# CHECK: crc32l %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32l %r18d, %r22d
+
+# CHECK: crc32q %r19, %r23
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32q %r19, %r23
+
+# CHECK: crc32w 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32w 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32l 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32b 291(%r28,%r29,4), %r19
+
+# CHECK: crc32q 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32q 291(%r28,%r29,4), %r19
+
+# CHECK: crc32b %r16b, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32b %r16b, %r22d
+
+# CHECK: crc32b %r16b, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32b %r16b, %r23
+
+# CHECK: crc32w %r17w, %r22d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32w %r17w, %r22d
+
+# CHECK: crc32l %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32l %r18d, %r22d
+
+# CHECK: crc32q %r19, %r23
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32q %r19, %r23
+
+# CHECK: crc32w 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32w 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32l 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32b 291(%r28,%r29,4), %r19
+
+# CHECK: crc32q 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32q 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/crc32-intel.s b/llvm/test/MC/X86/apx/crc32-intel.s
new file mode 100644
index 00000000000000..df974894d34662
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-intel.s
@@ -0,0 +1,73 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: crc32 r22d, r16b
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32 r22d, r16b
+
+# CHECK: crc32 r23, r16b
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32 r23, r16b
+
+# CHECK: crc32 r22d, r17w
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32 r22d, r17w
+
+# CHECK: crc32 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32 r22d, r18d
+
+# CHECK: crc32 r23, r19
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32 r23, r19
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, word ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, byte ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, qword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r22d, r16b
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32 r22d, r16b
+
+# CHECK: crc32 r23, r16b
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32 r23, r16b
+
+# CHECK: crc32 r22d, r17w
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32 r22d, r17w
+
+# CHECK: crc32 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32 r22d, r18d
+
+# CHECK: crc32 r23, r19
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32 r23, r19
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, word ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, byte ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index cb1a40d541537c..68d375ec3e4cd5 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -29,7 +29,7 @@
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 3 (Reg:xmm5): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
// CHECK: Opcode result: complete match, selecting this opcode
-// CHECK: AsmMatcher: found 2 encodings with mnemonic 'crc32l'
+// CHECK: AsmMatcher: found 4 encodings with mnemonic 'crc32l'
// CHECK: Trying to match opcode CRC32r32r32
// CHECK: Matching formal operand class MCK_GR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rbx,IndexReg=rcx,Scale=8,Disp=2125315823,SegReg=gs): Opcode result: multiple operand mismatches, ignoring this opcode
// CHECK: Trying to match opcode CRC32r32m32
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 4f957d104d8dd1..42b35721b3dd8c 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -1371,10 +1371,15 @@ static const X86FoldTableEntry Table2[] = {
{X86::CMPSSrr, X86::CMPSSrm, 0},
{X86::CMPSSrr_Int, X86::CMPSSrm_Int, TB_NO_REVERSE},
{X86::CRC32r32r16, X86::CRC32r32m16, 0},
+ {X86::CRC32r32r16_EVEX, X86::CRC32r32m16_EVEX, 0},
{X86::CRC32r32r32, X86::CRC32r32m32, 0},
+ {X86::CRC32r32r32_EVEX, X86::CRC32r32m32_EVEX, 0},
{X86::CRC32r32r8, X86::CRC32r32m8, 0},
+ {X86::CRC32r32r8_EVEX, X86::CRC32r32m8_EVEX, 0},
{X86::CRC32r64r64, X86::CRC32r64m64, 0},
+ {X86::CRC32r64r64_EVEX, X86::CRC32r64m64_EVEX, 0},
{X86::CRC32r64r8, X86::CRC32r64m8, 0},
+ {X86::CRC32r64r8_EVEX, X86::CRC32r64m8_EVEX, 0},
{X86::CVTSD2SSrr_Int, X86::CVTSD2SSrm_Int, TB_NO_REVERSE},
{X86::CVTSI2SDrr_Int, X86::CVTSI2SDrm_Int, 0},
{X86::CVTSI2SSrr_Int, X86::CVTSI2SSrm_Int, 0},
>From 0c27846e44123bc12c998856df55c3666d6ff9d5 Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 27 Dec 2023 23:17:23 -0800
Subject: [PATCH 2/2] resolve comments
---
llvm/lib/Target/X86/X86InstrSSE.td | 22 ++++---
llvm/test/MC/Disassembler/X86/apx/crc32.txt | 70 ++++++++++++--------
llvm/test/MC/X86/apx/crc32-att.s | 73 +++++++++++++--------
llvm/test/MC/X86/apx/crc32-intel.s | 70 ++++++++++++--------
4 files changed, 144 insertions(+), 91 deletions(-)
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index 60555c13125fc1..9da8b5684e829c 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6699,28 +6699,30 @@ let Constraints = "$src1 = $dst" in {
null_frag>, REX_W;
}
+ let Predicates = [In64BitMode] in {
def CRC32r32m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
- int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ int_x86_sse42_crc32_32_8>, EVEX, NoCD8, T_MAP4, PS;
def CRC32r32r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
- int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ int_x86_sse42_crc32_32_8>, EVEX, NoCD8, T_MAP4, PS;
def CRC32r32m16_EVEX : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
- int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ int_x86_sse42_crc32_32_16>, EVEX, NoCD8, T_MAP4, PD;
def CRC32r32r16_EVEX : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
- int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ int_x86_sse42_crc32_32_16>, EVEX, NoCD8, T_MAP4, PD;
def CRC32r32m32_EVEX : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
- int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ int_x86_sse42_crc32_32_32>, EVEX, NoCD8, T_MAP4, PS;
def CRC32r32r32_EVEX : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
- int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ int_x86_sse42_crc32_32_32>, EVEX, NoCD8, T_MAP4, PS;
def CRC32r64m64_EVEX : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
- int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, NoCD8, T_MAP4, PD;
def CRC32r64r64_EVEX : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
- int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, NoCD8, T_MAP4, PD;
let hasSideEffects = 0 in {
let mayLoad = 1 in
def CRC32r64m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
- null_frag>, REX_W, EVEX, T_MAP4, PS;
+ null_frag>, REX_W, EVEX, NoCD8, T_MAP4, PS;
def CRC32r64r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
- null_frag>, REX_W, EVEX, T_MAP4, PS;
+ null_frag>, REX_W, EVEX, NoCD8, T_MAP4, PS;
+ }
}
}
diff --git a/llvm/test/MC/Disassembler/X86/apx/crc32.txt b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
index 954fdbcdedcbd4..a8961401828168 100644
--- a/llvm/test/MC/Disassembler/X86/apx/crc32.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
@@ -1,41 +1,41 @@
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
-# ATT: crc32b %r16b, %r22d
-# INTEL: crc32 r22d, r16b
-0x62,0xec,0x7c,0x08,0xf0,0xf0
+# ATT: crc32b %al, %ebx
+# INTEL: crc32 ebx, al
+0x62,0xf4,0x7c,0x08,0xf0,0xd8
-# ATT: crc32b %r16b, %r23
-# INTEL: crc32 r23, r16b
-0x62,0xec,0xfc,0x08,0xf0,0xf8
+# ATT: crc32b %al, %rbx
+# INTEL: crc32 rbx, al
+0x62,0xf4,0xfc,0x08,0xf0,0xd8
-# ATT: crc32w %r17w, %r22d
-# INTEL: crc32 r22d, r17w
-0x62,0xec,0x7d,0x08,0xf1,0xf1
+# ATT: crc32w %ax, %ebx
+# INTEL: crc32 ebx, ax
+0x62,0xf4,0x7d,0x08,0xf1,0xd8
-# ATT: crc32l %r18d, %r22d
-# INTEL: crc32 r22d, r18d
-0x62,0xec,0x7c,0x08,0xf1,0xf2
+# ATT: crc32l %eax, %ebx
+# INTEL: crc32 ebx, eax
+0x62,0xf4,0x7c,0x08,0xf1,0xd8
-# ATT: crc32q %r19, %r23
-# INTEL: crc32 r23, r19
-0x62,0xec,0xfd,0x08,0xf1,0xfb
+# ATT: crc32q %rax, %rbx
+# INTEL: crc32 rbx, rax
+0x62,0xf4,0xfd,0x08,0xf1,0xd8
-# ATT: crc32w 291(%r28,%r29,4), %r18d
-# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
-0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+# ATT: crc32w 291(%rax,%rbx,4), %ecx
+# INTEL: crc32 ecx, word ptr [rax + 4*rbx + 291]
+0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
-# ATT: crc32l 291(%r28,%r29,4), %r18d
-# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
-0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+# ATT: crc32l 291(%rax,%rbx,4), %ecx
+# INTEL: crc32 ecx, dword ptr [rax + 4*rbx + 291]
+0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
-# ATT: crc32b 291(%r28,%r29,4), %r19
-# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
-0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+# ATT: crc32b 291(%rax,%rbx,4), %rcx
+# INTEL: crc32 rcx, byte ptr [rax + 4*rbx + 291]
+0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00
-# ATT: crc32q 291(%r28,%r29,4), %r19
-# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
-0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
+# ATT: crc32q 291(%rax,%rbx,4), %rcx
+# INTEL: crc32 rcx, qword ptr [rax + 4*rbx + 291]
+0x62,0xf4,0xfd,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00
# ATT: crc32b %r16b, %r22d
# INTEL: crc32 r22d, r16b
@@ -72,3 +72,19 @@
# ATT: crc32q 291(%r28,%r29,4), %r19
# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32w 123(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b
+
+# ATT: crc32l 123(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b
+
+# ATT: crc32b 123(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b
+
+# ATT: crc32q 123(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 123]
+0x62,0x8c,0xf9,0x08,0xf1,0x5c,0xac,0x7b
diff --git a/llvm/test/MC/X86/apx/crc32-att.s b/llvm/test/MC/X86/apx/crc32-att.s
index 5477f913e24e22..4c5a0702556381 100644
--- a/llvm/test/MC/X86/apx/crc32-att.s
+++ b/llvm/test/MC/X86/apx/crc32-att.s
@@ -1,40 +1,43 @@
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
-# CHECK: crc32b %r16b, %r22d
-# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
- crc32b %r16b, %r22d
+# ERROR-COUNT-22: error:
+# ERROR-NOT: error:
+# CHECK: {evex} crc32b %al, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xd8]
+ {evex} crc32b %al, %ebx
-# CHECK: crc32b %r16b, %r23
-# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
- crc32b %r16b, %r23
+# CHECK: {evex} crc32b %al, %rbx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0xd8]
+ {evex} crc32b %al, %rbx
-# CHECK: crc32w %r17w, %r22d
-# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
- crc32w %r17w, %r22d
+# CHECK: {evex} crc32w %ax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xd8]
+ {evex} crc32w %ax, %ebx
-# CHECK: crc32l %r18d, %r22d
-# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
- crc32l %r18d, %r22d
+# CHECK: {evex} crc32l %eax, %ebx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xd8]
+ {evex} crc32l %eax, %ebx
-# CHECK: crc32q %r19, %r23
-# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
- crc32q %r19, %r23
+# CHECK: {evex} crc32q %rax, %rbx
+# CHECK: encoding: [0x62,0xf4,0xfd,0x08,0xf1,0xd8]
+ {evex} crc32q %rax, %rbx
-# CHECK: crc32w 291(%r28,%r29,4), %r18d
-# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
- crc32w 291(%r28,%r29,4), %r18d
+# CHECK: {evex} crc32w 291(%rax,%rbx,4), %ecx
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32w 291(%rax,%rbx,4), %ecx
-# CHECK: crc32l 291(%r28,%r29,4), %r18d
-# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
- crc32l 291(%r28,%r29,4), %r18d
+# CHECK: {evex} crc32l 291(%rax,%rbx,4), %ecx
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32l 291(%rax,%rbx,4), %ecx
-# CHECK: crc32b 291(%r28,%r29,4), %r19
-# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
- crc32b 291(%r28,%r29,4), %r19
+# CHECK: {evex} crc32b 291(%rax,%rbx,4), %rcx
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32b 291(%rax,%rbx,4), %rcx
-# CHECK: crc32q 291(%r28,%r29,4), %r19
-# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
- crc32q 291(%r28,%r29,4), %r19
+# CHECK: {evex} crc32q 291(%rax,%rbx,4), %rcx
+# CHECK: encoding: [0x62,0xf4,0xfd,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32q 291(%rax,%rbx,4), %rcx
# CHECK: crc32b %r16b, %r22d
# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
@@ -71,3 +74,19 @@
# CHECK: crc32q 291(%r28,%r29,4), %r19
# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
crc32q 291(%r28,%r29,4), %r19
+
+# CHECK: crc32w 123(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b]
+ crc32w 123(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 123(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b]
+ crc32l 123(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 123(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b]
+ crc32b 123(%r28,%r29,4), %r19
+
+# CHECK: crc32q 123(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x5c,0xac,0x7b]
+ crc32q 123(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/crc32-intel.s b/llvm/test/MC/X86/apx/crc32-intel.s
index df974894d34662..f0af35691be329 100644
--- a/llvm/test/MC/X86/apx/crc32-intel.s
+++ b/llvm/test/MC/X86/apx/crc32-intel.s
@@ -1,40 +1,40 @@
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
-# CHECK: crc32 r22d, r16b
-# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
- crc32 r22d, r16b
+# CHECK: {evex} crc32 ebx, al
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf0,0xd8]
+ {evex} crc32 ebx, al
-# CHECK: crc32 r23, r16b
-# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
- crc32 r23, r16b
+# CHECK: {evex} crc32 rbx, al
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0xd8]
+ {evex} crc32 rbx, al
-# CHECK: crc32 r22d, r17w
-# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
- crc32 r22d, r17w
+# CHECK: {evex} crc32 ebx, ax
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xd8]
+ {evex} crc32 ebx, ax
-# CHECK: crc32 r22d, r18d
-# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
- crc32 r22d, r18d
+# CHECK: {evex} crc32 ebx, eax
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0xd8]
+ {evex} crc32 ebx, eax
-# CHECK: crc32 r23, r19
-# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
- crc32 r23, r19
+# CHECK: {evex} crc32 rbx, rax
+# CHECK: encoding: [0x62,0xf4,0xfd,0x08,0xf1,0xd8]
+ {evex} crc32 rbx, rax
-# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
- crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: {evex} crc32 ecx, word ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 ecx, word ptr [rax + 4*rbx + 291]
-# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
- crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: {evex} crc32 ecx, dword ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 ecx, dword ptr [rax + 4*rbx + 291]
-# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
- crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: {evex} crc32 rcx, byte ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0xfc,0x08,0xf0,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 rcx, byte ptr [rax + 4*rbx + 291]
-# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
-# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
- crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: {evex} crc32 rcx, qword ptr [rax + 4*rbx + 291]
+# CHECK: encoding: [0x62,0xf4,0xfd,0x08,0xf1,0x8c,0x98,0x23,0x01,0x00,0x00]
+ {evex} crc32 rcx, qword ptr [rax + 4*rbx + 291]
# CHECK: crc32 r22d, r16b
# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
@@ -71,3 +71,19 @@
# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
crc32 r19, qword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x54,0xac,0x7b]
+ crc32 r18d, word ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x54,0xac,0x7b]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x5c,0xac,0x7b]
+ crc32 r19, byte ptr [r28 + 4*r29 + 123]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 123]
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x5c,0xac,0x7b]
+ crc32 r19, qword ptr [r28 + 4*r29 + 123]
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