[llvm] [X86][MC] Support Enc/Dec for EGPR for promoted CRC32 (PR #76434)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 27 02:41:53 PST 2023
https://github.com/XinWang10 created https://github.com/llvm/llvm-project/pull/76434
R16-R31 was added into GPRs in https://github.com/llvm/llvm-project/pull/70958,
This patch supports the encoding/decoding for promoted CRC32 instruction in EVEX space.
RFC: https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
>From 74421860e635d3ffcce1d4c14adf4f285f3e2fad Mon Sep 17 00:00:00 2001
From: "Wang, Xin10" <xin10.wang at intel.com>
Date: Wed, 27 Dec 2023 02:40:39 -0800
Subject: [PATCH] [X86][MC] Support Enc/Dec for EGPR for promoted CRC32
---
llvm/lib/Target/X86/X86InstrSSE.td | 24 +++++++
llvm/test/MC/Disassembler/X86/apx/crc32.txt | 74 +++++++++++++++++++++
llvm/test/MC/X86/apx/crc32-att.s | 73 ++++++++++++++++++++
llvm/test/MC/X86/apx/crc32-intel.s | 73 ++++++++++++++++++++
llvm/test/MC/X86/x86_64-asm-match.s | 2 +-
llvm/test/TableGen/x86-fold-tables.inc | 5 ++
6 files changed, 250 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/MC/Disassembler/X86/apx/crc32.txt
create mode 100644 llvm/test/MC/X86/apx/crc32-att.s
create mode 100644 llvm/test/MC/X86/apx/crc32-intel.s
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index df1f0b5b4ca727..60555c13125fc1 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -6698,6 +6698,30 @@ let Constraints = "$src1 = $dst" in {
def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
null_frag>, REX_W;
}
+
+ def CRC32r32m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
+ int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ def CRC32r32r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
+ int_x86_sse42_crc32_32_8>, EVEX, T_MAP4, PS;
+ def CRC32r32m16_EVEX : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
+ int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ def CRC32r32r16_EVEX : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
+ int_x86_sse42_crc32_32_16>, EVEX, T_MAP4, PD;
+ def CRC32r32m32_EVEX : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
+ int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ def CRC32r32r32_EVEX : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
+ int_x86_sse42_crc32_32_32>, EVEX, T_MAP4, PS;
+ def CRC32r64m64_EVEX : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ def CRC32r64r64_EVEX : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
+ int_x86_sse42_crc32_64_64>, REX_W, EVEX, T_MAP4, PD;
+ let hasSideEffects = 0 in {
+ let mayLoad = 1 in
+ def CRC32r64m8_EVEX : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
+ null_frag>, REX_W, EVEX, T_MAP4, PS;
+ def CRC32r64r8_EVEX : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
+ null_frag>, REX_W, EVEX, T_MAP4, PS;
+ }
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/X86/apx/crc32.txt b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
new file mode 100644
index 00000000000000..954fdbcdedcbd4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/X86/apx/crc32.txt
@@ -0,0 +1,74 @@
+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT: crc32b %r16b, %r22d
+# INTEL: crc32 r22d, r16b
+0x62,0xec,0x7c,0x08,0xf0,0xf0
+
+# ATT: crc32b %r16b, %r23
+# INTEL: crc32 r23, r16b
+0x62,0xec,0xfc,0x08,0xf0,0xf8
+
+# ATT: crc32w %r17w, %r22d
+# INTEL: crc32 r22d, r17w
+0x62,0xec,0x7d,0x08,0xf1,0xf1
+
+# ATT: crc32l %r18d, %r22d
+# INTEL: crc32 r22d, r18d
+0x62,0xec,0x7c,0x08,0xf1,0xf2
+
+# ATT: crc32q %r19, %r23
+# INTEL: crc32 r23, r19
+0x62,0xec,0xfd,0x08,0xf1,0xfb
+
+# ATT: crc32w 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b %r16b, %r22d
+# INTEL: crc32 r22d, r16b
+0x62,0xec,0x7c,0x08,0xf0,0xf0
+
+# ATT: crc32b %r16b, %r23
+# INTEL: crc32 r23, r16b
+0x62,0xec,0xfc,0x08,0xf0,0xf8
+
+# ATT: crc32w %r17w, %r22d
+# INTEL: crc32 r22d, r17w
+0x62,0xec,0x7d,0x08,0xf1,0xf1
+
+# ATT: crc32l %r18d, %r22d
+# INTEL: crc32 r22d, r18d
+0x62,0xec,0x7c,0x08,0xf1,0xf2
+
+# ATT: crc32q %r19, %r23
+# INTEL: crc32 r23, r19
+0x62,0xec,0xfd,0x08,0xf1,0xfb
+
+# ATT: crc32w 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32l 291(%r28,%r29,4), %r18d
+# INTEL: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32b 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00
+
+# ATT: crc32q 291(%r28,%r29,4), %r19
+# INTEL: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00
diff --git a/llvm/test/MC/X86/apx/crc32-att.s b/llvm/test/MC/X86/apx/crc32-att.s
new file mode 100644
index 00000000000000..5477f913e24e22
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-att.s
@@ -0,0 +1,73 @@
+# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+# CHECK: crc32b %r16b, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32b %r16b, %r22d
+
+# CHECK: crc32b %r16b, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32b %r16b, %r23
+
+# CHECK: crc32w %r17w, %r22d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32w %r17w, %r22d
+
+# CHECK: crc32l %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32l %r18d, %r22d
+
+# CHECK: crc32q %r19, %r23
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32q %r19, %r23
+
+# CHECK: crc32w 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32w 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32l 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32b 291(%r28,%r29,4), %r19
+
+# CHECK: crc32q 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32q 291(%r28,%r29,4), %r19
+
+# CHECK: crc32b %r16b, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32b %r16b, %r22d
+
+# CHECK: crc32b %r16b, %r23
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32b %r16b, %r23
+
+# CHECK: crc32w %r17w, %r22d
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32w %r17w, %r22d
+
+# CHECK: crc32l %r18d, %r22d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32l %r18d, %r22d
+
+# CHECK: crc32q %r19, %r23
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32q %r19, %r23
+
+# CHECK: crc32w 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32w 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32l 291(%r28,%r29,4), %r18d
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32l 291(%r28,%r29,4), %r18d
+
+# CHECK: crc32b 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32b 291(%r28,%r29,4), %r19
+
+# CHECK: crc32q 291(%r28,%r29,4), %r19
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32q 291(%r28,%r29,4), %r19
diff --git a/llvm/test/MC/X86/apx/crc32-intel.s b/llvm/test/MC/X86/apx/crc32-intel.s
new file mode 100644
index 00000000000000..df974894d34662
--- /dev/null
+++ b/llvm/test/MC/X86/apx/crc32-intel.s
@@ -0,0 +1,73 @@
+# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+# CHECK: crc32 r22d, r16b
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32 r22d, r16b
+
+# CHECK: crc32 r23, r16b
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32 r23, r16b
+
+# CHECK: crc32 r22d, r17w
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32 r22d, r17w
+
+# CHECK: crc32 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32 r22d, r18d
+
+# CHECK: crc32 r23, r19
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32 r23, r19
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, word ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, byte ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, qword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r22d, r16b
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf0,0xf0]
+ crc32 r22d, r16b
+
+# CHECK: crc32 r23, r16b
+# CHECK: encoding: [0x62,0xec,0xfc,0x08,0xf0,0xf8]
+ crc32 r23, r16b
+
+# CHECK: crc32 r22d, r17w
+# CHECK: encoding: [0x62,0xec,0x7d,0x08,0xf1,0xf1]
+ crc32 r22d, r17w
+
+# CHECK: crc32 r22d, r18d
+# CHECK: encoding: [0x62,0xec,0x7c,0x08,0xf1,0xf2]
+ crc32 r22d, r18d
+
+# CHECK: crc32 r23, r19
+# CHECK: encoding: [0x62,0xec,0xfd,0x08,0xf1,0xfb]
+ crc32 r23, r19
+
+# CHECK: crc32 r18d, word ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x79,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, word ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0x78,0x08,0xf1,0x94,0xac,0x23,0x01,0x00,0x00]
+ crc32 r18d, dword ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, byte ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf8,0x08,0xf0,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, byte ptr [r28 + 4*r29 + 291]
+
+# CHECK: crc32 r19, qword ptr [r28 + 4*r29 + 291]
+# CHECK: encoding: [0x62,0x8c,0xf9,0x08,0xf1,0x9c,0xac,0x23,0x01,0x00,0x00]
+ crc32 r19, qword ptr [r28 + 4*r29 + 291]
diff --git a/llvm/test/MC/X86/x86_64-asm-match.s b/llvm/test/MC/X86/x86_64-asm-match.s
index cb1a40d541537c..68d375ec3e4cd5 100644
--- a/llvm/test/MC/X86/x86_64-asm-match.s
+++ b/llvm/test/MC/X86/x86_64-asm-match.s
@@ -29,7 +29,7 @@
// CHECK: Matching formal operand class MCK_FR16 against actual operand at index 3 (Reg:xmm5): match success using generic matcher
// CHECK: Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range
// CHECK: Opcode result: complete match, selecting this opcode
-// CHECK: AsmMatcher: found 2 encodings with mnemonic 'crc32l'
+// CHECK: AsmMatcher: found 4 encodings with mnemonic 'crc32l'
// CHECK: Trying to match opcode CRC32r32r32
// CHECK: Matching formal operand class MCK_GR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=rbx,IndexReg=rcx,Scale=8,Disp=2125315823,SegReg=gs): Opcode result: multiple operand mismatches, ignoring this opcode
// CHECK: Trying to match opcode CRC32r32m32
diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc
index 4f957d104d8dd1..42b35721b3dd8c 100644
--- a/llvm/test/TableGen/x86-fold-tables.inc
+++ b/llvm/test/TableGen/x86-fold-tables.inc
@@ -1371,10 +1371,15 @@ static const X86FoldTableEntry Table2[] = {
{X86::CMPSSrr, X86::CMPSSrm, 0},
{X86::CMPSSrr_Int, X86::CMPSSrm_Int, TB_NO_REVERSE},
{X86::CRC32r32r16, X86::CRC32r32m16, 0},
+ {X86::CRC32r32r16_EVEX, X86::CRC32r32m16_EVEX, 0},
{X86::CRC32r32r32, X86::CRC32r32m32, 0},
+ {X86::CRC32r32r32_EVEX, X86::CRC32r32m32_EVEX, 0},
{X86::CRC32r32r8, X86::CRC32r32m8, 0},
+ {X86::CRC32r32r8_EVEX, X86::CRC32r32m8_EVEX, 0},
{X86::CRC32r64r64, X86::CRC32r64m64, 0},
+ {X86::CRC32r64r64_EVEX, X86::CRC32r64m64_EVEX, 0},
{X86::CRC32r64r8, X86::CRC32r64m8, 0},
+ {X86::CRC32r64r8_EVEX, X86::CRC32r64m8_EVEX, 0},
{X86::CVTSD2SSrr_Int, X86::CVTSD2SSrm_Int, TB_NO_REVERSE},
{X86::CVTSI2SDrr_Int, X86::CVTSI2SDrm_Int, 0},
{X86::CVTSI2SSrr_Int, X86::CVTSI2SSrm_Int, 0},
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