[llvm] [X86][MC] Support encoding/decoding for APX variant ADD/SUB/ADC/SBB/OR/XOR instructions (PR #76319)

[Shengchen Kan via llvm-commits]

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@@ -3996,6 +4001,8 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(MCID))
     return Match_Unsupported;
+  if (ForcedNoFlag != static_cast<bool>(MCID.TSFlags & X86II::EVEX_NF))
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KanRobert wrote:

NF instruction and non-NF instruction shares the same asm string in the TD file.
Fonr non `{nf}` asm, `ForceNoFlag = false`, 
for NF instruction,  `(MCID.TSFlags & X86II::EVEX_NF) = true`.
 
They're not equal. So non `{nf}` asm can only match non-NF instruction.

https://github.com/llvm/llvm-project/pull/76319