[llvm] [X86][MC] Support encoding/decoding for APX variant ADD/SUB/ADC/SBB/OR/XOR instructions (PR #76319)

[Phoebe Wang via llvm-commits]

================
@@ -3996,6 +4001,8 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
 
   if (UseApxExtendedReg && !X86II::canUseApxExtendedReg(MCID))
     return Match_Unsupported;
+  if (ForcedNoFlag != static_cast<bool>(MCID.TSFlags & X86II::EVEX_NF))
----------------
phoebewang wrote:

Why a not `{nf}` assembly can be matched to {nf} instruction? If you want to check for unexpected case, you can use an assert here.

https://github.com/llvm/llvm-project/pull/76319