[llvm] 256bf56 - [RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)

[via llvm-commits]

Author: Yeting Kuo
Date: 2023-12-27T09:11:34+08:00
New Revision: 256bf56afa58679b50a72b69c0e2a4d198d42247

URL: https://github.com/llvm/llvm-project/commit/256bf56afa58679b50a72b69c0e2a4d198d42247
DIFF: https://github.com/llvm/llvm-project/commit/256bf56afa58679b50a72b69c0e2a4d198d42247.diff

LOG: [RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)

he spimm operand is an immediate whose only 4-5th bit could be setted
and not based on rlist operand

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 53e2b6b4d94ea0..184000b48987e6 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -462,10 +462,8 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
   return MCDisassembler::Success;
 }
 
-// spimm is based on rlist now.
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
-  // TODO: check if spimm matches rlist
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index 9a7249fe3e3d6c..3506204d6c2553 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -69,7 +69,7 @@ def spimm : Operand<OtherVT> {
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    return isShiftedUInt<5, 4>(Imm);
+    return isShiftedUInt<2, 4>(Imm);
   }];
 }