[llvm] b996f84 - [RISCV][NFC] Refine MCOperandPredicate code for rtlist. (#76028)

[via llvm-commits]

Author: Yeting Kuo
Date: 2023-12-26T17:13:05+08:00
New Revision: b996f84bc421387a36effd2aa2fa1abad25d1762

URL: https://github.com/llvm/llvm-project/commit/b996f84bc421387a36effd2aa2fa1abad25d1762
DIFF: https://github.com/llvm/llvm-project/commit/b996f84bc421387a36effd2aa2fa1abad25d1762.diff

LOG: [RISCV][NFC] Refine MCOperandPredicate code for rtlist. (#76028)

(Imm <= 15) could be implied by isUInt<4>(Imm).

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZc.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
index a78f3624446871..9a7249fe3e3d6c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -56,9 +56,8 @@ def rlist : Operand<OtherVT> {
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    if (!isUInt<4>(Imm)) return false;
     // 0~3 Reserved for EABI
-    return (Imm >= 4) && (Imm <= 15);
+    return isUInt<4>(Imm) && Imm >= 4;
   }];
  }