[llvm] [RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (PR #76061)

[Craig Topper via llvm-commits]

================
@@ -462,10 +462,10 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
   return MCDisassembler::Success;
 }
 
-// spimm is based on rlist now.
 static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm,
                                     uint64_t Address, const void *Decoder) {
-  // TODO: check if spimm matches rlist
+  if (!isShiftedUInt<2, 4>(Imm))
----------------
topperc wrote:

I don't this check can ever fail. The caller looks like

```
    tmp = fieldFromInstruction(insn, 2, 2) << 4;                                 
    if (!Check(S, decodeZcmpSpimm(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
```

So its guaranteed to be a `isShiftedUInt<2, 4>`



https://github.com/llvm/llvm-project/pull/76061