[llvm] [RISCV][DAG] Teach computeKnownBits consider SEW/LMUL/AVL for vsetvli. (PR #76158)

Yeting Kuo via llvm-commits llvm-commits at lists.llvm.org
Sun Dec 24 19:18:29 PST 2023

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https://github.com/yetingk closed https://github.com/llvm/llvm-project/pull/76158

Previous message: [llvm] [RISCV][DAG] Teach computeKnownBits consider SEW/LMUL/AVL for vsetvli. (PR #76158)
Next message: [llvm] [clang-tools-extra] [clang] [Clang][SME2] Enable multi-vector loads & stores for SME2 (PR #75821)
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