[llvm] [CostModel][X86] Fix fpext conversion cost for 16 elements (PR #76278)
via llvm-commits
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Fri Dec 22 21:33:44 PST 2023
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git-clang-format --diff 2205d2334f3c859ad9f6c65ed950bfb3bb6f7cbe 90c9efc967dd02a37ebf2abf0c771011ae670dea -- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
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diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index e7b7c9666e..4b68ccdcae 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -2221,140 +2221,141 @@ InstructionCost X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
// 256-bit wide vectors.
static const TypeConversionCostTblEntry AVX512FConversionTbl[] = {
- { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
- { ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3 },
- { ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32, 5 }, // 2*vcvtps2pd+vextractf64x4
- { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
-
- { ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3 }, // sext+vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3 }, // sext+vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3 }, // sext+vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3 }, // sext+vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3 }, // sext+vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3 }, // sext+vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2 }, // zmm vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2 }, // zmm vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2 }, // vpslld+vptestmd
- { ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2 }, // zmm vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2 }, // zmm vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2 }, // vpsllq+vptestmq
- { ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2 }, // vpmovdb
- { ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2 }, // vpmovdb
- { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2 }, // vpmovdb
- { ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2 }, // vpmovdb
- { ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2 }, // vpmovdb
- { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2 }, // vpmovdw
- { ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2 }, // vpmovdw
- { ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2 }, // vpmovqb
- { ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1 }, // vpshufb
- { ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2 }, // vpmovqb
- { ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2 }, // vpmovqb
- { ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2 }, // vpmovqb
- { ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2 }, // vpmovqb
- { ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2 }, // vpmovqw
- { ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2 }, // vpmovqw
- { ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2 }, // vpmovqw
- { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1 }, // vpmovqd
- { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 }, // zmm vpmovqd
- { ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5 },// 2*vpmovqd+concat+vpmovdb
-
- { ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3 }, // extend to v16i32
- { ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8 },
- { ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8 },
-
- // Sign extend is zmm vpternlogd+vptruncdb.
- // Zero extend is zmm broadcast load+vptruncdw.
- { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4 },
-
- // Sign extend is zmm vpternlogd+vptruncdw.
- // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
- { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4 },
- { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3 },
- { ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4 },
-
- { ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1 }, // zmm vpternlogd
- { ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2 }, // zmm vpternlogd+psrld
- { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1 }, // zmm vpternlogd
- { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2 }, // zmm vpternlogd+psrld
- { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1 }, // zmm vpternlogd
- { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2 }, // zmm vpternlogd+psrld
- { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1 }, // zmm vpternlogq
- { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2 }, // zmm vpternlogq+psrlq
- { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1 }, // zmm vpternlogq
- { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2 }, // zmm vpternlogq+psrlq
-
- { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1 }, // vpternlogd
- { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, // vpternlogd+psrld
- { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1 }, // vpternlogq
- { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2 }, // vpternlogq+psrlq
-
- { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
- { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
- { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
- { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1 },
- { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
- { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1 },
- { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
- { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1 },
- { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
- { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1 },
-
- { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
- { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3 }, // FIXME: May not be right
-
- { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
- { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
- { ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 },
- { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 },
- { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
- { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 },
- { ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
- { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
-
- { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 },
- { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 },
- { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 },
- { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 },
- { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 },
- { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 },
- { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 },
- { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 },
- { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26 },
- { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
-
- { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2 },
- { ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7 },
- { ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64,15 },
- { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32,11 },
- { ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64,31 },
- { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3 },
- { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7 },
- { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5 },
- { ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64,15 },
- { ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1 },
- { ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3 },
-
- { ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1 },
- { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3 },
- { ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3 },
- { ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1 },
- { ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3 },
- { ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3 },
+ {ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1},
+ {ISD::FP_EXTEND, MVT::v8f64, MVT::v16f32, 3},
+ {ISD::FP_EXTEND, MVT::v16f64, MVT::v16f32,
+ 5}, // 2*vcvtps2pd+vextractf64x4
+ {ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1},
+
+ {ISD::TRUNCATE, MVT::v2i1, MVT::v2i8, 3}, // sext+vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v4i1, MVT::v4i8, 3}, // sext+vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3}, // sext+vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v16i1, MVT::v16i8, 3}, // sext+vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v2i1, MVT::v2i16, 3}, // sext+vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v4i1, MVT::v4i16, 3}, // sext+vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3}, // sext+vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v16i1, MVT::v16i16, 3}, // sext+vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v2i1, MVT::v2i32, 2}, // zmm vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v4i1, MVT::v4i32, 2}, // zmm vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2}, // zmm vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v16i1, MVT::v16i32, 2}, // vpslld+vptestmd
+ {ISD::TRUNCATE, MVT::v2i1, MVT::v2i64, 2}, // zmm vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v4i1, MVT::v4i64, 2}, // zmm vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v8i1, MVT::v8i64, 2}, // vpsllq+vptestmq
+ {ISD::TRUNCATE, MVT::v2i8, MVT::v2i32, 2}, // vpmovdb
+ {ISD::TRUNCATE, MVT::v4i8, MVT::v4i32, 2}, // vpmovdb
+ {ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 2}, // vpmovdb
+ {ISD::TRUNCATE, MVT::v32i8, MVT::v16i32, 2}, // vpmovdb
+ {ISD::TRUNCATE, MVT::v64i8, MVT::v16i32, 2}, // vpmovdb
+ {ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 2}, // vpmovdw
+ {ISD::TRUNCATE, MVT::v32i16, MVT::v16i32, 2}, // vpmovdw
+ {ISD::TRUNCATE, MVT::v2i8, MVT::v2i64, 2}, // vpmovqb
+ {ISD::TRUNCATE, MVT::v2i16, MVT::v2i64, 1}, // vpshufb
+ {ISD::TRUNCATE, MVT::v8i8, MVT::v8i64, 2}, // vpmovqb
+ {ISD::TRUNCATE, MVT::v16i8, MVT::v8i64, 2}, // vpmovqb
+ {ISD::TRUNCATE, MVT::v32i8, MVT::v8i64, 2}, // vpmovqb
+ {ISD::TRUNCATE, MVT::v64i8, MVT::v8i64, 2}, // vpmovqb
+ {ISD::TRUNCATE, MVT::v8i16, MVT::v8i64, 2}, // vpmovqw
+ {ISD::TRUNCATE, MVT::v16i16, MVT::v8i64, 2}, // vpmovqw
+ {ISD::TRUNCATE, MVT::v32i16, MVT::v8i64, 2}, // vpmovqw
+ {ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 1}, // vpmovqd
+ {ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1}, // zmm vpmovqd
+ {ISD::TRUNCATE, MVT::v16i8, MVT::v16i64, 5}, // 2*vpmovqd+concat+vpmovdb
+
+ {ISD::TRUNCATE, MVT::v16i8, MVT::v16i16, 3}, // extend to v16i32
+ {ISD::TRUNCATE, MVT::v32i8, MVT::v32i16, 8},
+ {ISD::TRUNCATE, MVT::v64i8, MVT::v32i16, 8},
+
+ // Sign extend is zmm vpternlogd+vptruncdb.
+ // Zero extend is zmm broadcast load+vptruncdw.
+ {ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v2i8, MVT::v2i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v4i8, MVT::v4i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v16i8, MVT::v16i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v16i8, MVT::v16i1, 4},
+
+ // Sign extend is zmm vpternlogd+vptruncdw.
+ // Zero extend is zmm vpternlogd+vptruncdw+vpsrlw.
+ {ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v2i16, MVT::v2i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 4},
+ {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i1, 3},
+ {ISD::ZERO_EXTEND, MVT::v16i16, MVT::v16i1, 4},
+
+ {ISD::SIGN_EXTEND, MVT::v2i32, MVT::v2i1, 1}, // zmm vpternlogd
+ {ISD::ZERO_EXTEND, MVT::v2i32, MVT::v2i1, 2}, // zmm vpternlogd+psrld
+ {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i1, 1}, // zmm vpternlogd
+ {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i1, 2}, // zmm vpternlogd+psrld
+ {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 1}, // zmm vpternlogd
+ {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 2}, // zmm vpternlogd+psrld
+ {ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i1, 1}, // zmm vpternlogq
+ {ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i1, 2}, // zmm vpternlogq+psrlq
+ {ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 1}, // zmm vpternlogq
+ {ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i1, 2}, // zmm vpternlogq+psrlq
+
+ {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 1}, // vpternlogd
+ {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2}, // vpternlogd+psrld
+ {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i1, 1}, // vpternlogq
+ {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i1, 2}, // vpternlogq+psrlq
+
+ {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1},
+ {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1},
+ {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1},
+ {ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i16, 1},
+ {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 1},
+ {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i8, 1},
+ {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 1},
+ {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 1},
+ {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i32, 1},
+ {ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i32, 1},
+
+ {ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, 3}, // FIXME: May not be right
+ {ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i8, 3}, // FIXME: May not be right
+
+ {ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i1, 4},
+ {ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3},
+ {ISD::SINT_TO_FP, MVT::v8f64, MVT::v16i8, 2},
+ {ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 1},
+ {ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i16, 2},
+ {ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 1},
+ {ISD::SINT_TO_FP, MVT::v8f64, MVT::v8i32, 1},
+ {ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 1},
+
+ {ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4},
+ {ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3},
+ {ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2},
+ {ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1},
+ {ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2},
+ {ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1},
+ {ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1},
+ {ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1},
+ {ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 26},
+ {ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5},
+
+ {ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f32, 2},
+ {ISD::FP_TO_SINT, MVT::v16i8, MVT::v16f64, 7},
+ {ISD::FP_TO_SINT, MVT::v32i8, MVT::v32f64, 15},
+ {ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f32, 11},
+ {ISD::FP_TO_SINT, MVT::v64i8, MVT::v64f64, 31},
+ {ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f64, 3},
+ {ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f64, 7},
+ {ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f32, 5},
+ {ISD::FP_TO_SINT, MVT::v32i16, MVT::v32f64, 15},
+ {ISD::FP_TO_SINT, MVT::v8i32, MVT::v8f64, 1},
+ {ISD::FP_TO_SINT, MVT::v16i32, MVT::v16f64, 3},
+
+ {ISD::FP_TO_UINT, MVT::v8i32, MVT::v8f64, 1},
+ {ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f64, 3},
+ {ISD::FP_TO_UINT, MVT::v8i8, MVT::v8f64, 3},
+ {ISD::FP_TO_UINT, MVT::v16i32, MVT::v16f32, 1},
+ {ISD::FP_TO_UINT, MVT::v16i16, MVT::v16f32, 3},
+ {ISD::FP_TO_UINT, MVT::v16i8, MVT::v16f32, 3},
};
static const TypeConversionCostTblEntry AVX512BWVLConversionTbl[] {
``````````
</details>
https://github.com/llvm/llvm-project/pull/76278
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