[llvm] [AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (PR #75832)

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git-clang-format --diff 966416b9e8e315494d586c5f0e88516e22135698 b19ef62fe97409f2bd40a980e6fa41461eb05b42 -- llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h llvm/include/llvm/CodeGen/GlobalISel/Utils.h llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/Target/AArch64/AArch64ISelLowering.h llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
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diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
index a450798c43..69a0dd5990 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
@@ -434,8 +434,7 @@ bool matchExtUaddvToUaddlv(MachineInstr &MI, MachineRegisterInfo &MRI,
   LLT ExtSrcTy = MRI.getType(ExtSrcReg);
   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
   if ((DstTy.getScalarSizeInBits() == 16 &&
-       ExtSrcTy.getNumElements() % 8 == 0 &&
-       ExtSrcTy.getNumElements() < 256) ||
+       ExtSrcTy.getNumElements() % 8 == 0 && ExtSrcTy.getNumElements() < 256) ||
       (DstTy.getScalarSizeInBits() == 32 &&
        ExtSrcTy.getNumElements() % 4 == 0 &&
        ExtSrcTy.getNumElements() < 65536) ||

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https://github.com/llvm/llvm-project/pull/75832