[llvm] [AMDGPU][True16] Fix the VGPR register class for 16-bit values. (PR #76170)

[Ivan Kosarev via llvm-commits]

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@@ -100,7 +100,9 @@ define amdgpu_kernel void @fadd_f16(
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX11-GISEL-NEXT:    buffer_load_u16 v1, off, s[0:3], 0 glc dlc
 ; GFX11-GISEL-NEXT:    s_waitcnt vmcnt(0)
-; GFX11-GISEL-NEXT:    v_add_f16_e32 v0.l, v0.l, v1.l
+; GFX11-GISEL-NEXT:    v_mov_b16_e32 v0.h, v1.l
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kosarev wrote:

It's a truncating copy and there are no any t16 operand folding changes here upstream yet nor RA hints, so I wouldn't expect the generic infrastructure to know anything about how to handle this better at the moment.

https://github.com/llvm/llvm-project/pull/76170