[llvm] [AMDGPU] Allocate i1 argument to SGPRs (PR #72461)

[Matt Arsenault via llvm-commits]

================
@@ -715,6 +715,14 @@ bool SILowerI1Copies::lowerCopiesToI1() {
       assert(!MI.getOperand(1).getSubReg());
 
       if (!SrcReg.isVirtual() || (!isLaneMaskReg(SrcReg) && !isVreg1(SrcReg))) {
+        if (!SrcReg.isVirtual() &&
+            TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 64) {
+          // When calling convention allocates SGPR for i1, for GPUs with
+          // wavefront size 64, i1 return value is put in 64b SGPR.
+          assert(ST->isWave64());
+          continue;
+        }
+
----------------
arsenm wrote:

Can you post the actual MIR you are getting? You really should not touch any code in SILowerI1Copies, you do not have the correct context here to know if you're doing something sensible.

callseq_end isn't associated with a value, it's just the SP modification and provides ordering. It's disconnected from the passed register value. In this context, the raw register copy is uniform, but the logical value is divergent. Coming of of the DAG for an incoming value, I would expect you to end up with something like:

```
  %0:sreg_64_exec = COPY $sgpr0_sgpr1 # This ABI copy should exist as-is
  %1:vreg_1 = COPY %0 # SILowerI1Copies is supposed to deal with this 
```

For the outgoing side, I would expect:

```
  %2:vreg_1 = ...
  %3:sreg_64_exec = COPY %2 
  $sgpr0_sgpr1 = COPY %3 # Untouchable ABI copy
```




https://github.com/llvm/llvm-project/pull/72461